C8051F130-GQR Silicon Laboratories Inc, C8051F130-GQR Datasheet - Page 345

• Manufacturer Part Number: C8051F130-GQR
• Description: IC 8051 MCU 128K FLASH 100TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F13xr

Specifications of C8051F130-GQR

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 64
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8.25K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Processor Series: C8051F1x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 8.25 KB
• Interface Type: I2C, SMBus, SPI, UART
• Maximum Clock Frequency: 100 MHz
• Number Of Programmable I/os: 64
• Number Of Timers: 5
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F120DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

This register determines how the Flash interface logic will respond to reads and writes to the FLASH-
Bit7:
Bits6–4: WRMD2–0: Write Mode Select Bits.
Bits3–0: RDMD3–0: Read Mode Select Bits.
SFLE
Bit7
JTAG Register Definition 25.3. FLASHCON: JTAG Flash Control
DAT Register.
SFLE: Scratchpad Flash Memory Access Enable
When this bit is set, Flash reads and writes are directed to the two 128-byte Scratchpad
Flash sectors. When SFLE is set to logic 1, Flash accesses out of the address range 0x00-
0xFF should not be attempted (with the exception of address 0x400, which can be used to
simultaneously erase both Scratchpad areas). Reads/Writes out of this range will yield
undefined results.
0: Flash access directed to the Program/Data Flash sector.
1: Flash access directed to the two 128 byte Scratchpad sectors.
The Write Mode Select Bits control how the interface logic responds to writes to the FLASH-
DAT Register per the following values:
000:
ignored.
001:
010:
(All other values for WRMD2-0 are reserved.)
The Read Mode Select Bits control how the interface logic responds to reads from the
FLASHDAT Register per the following values:
0000:
0001:
0010:
(All other values for RDMD3–0 are reserved.)
WRMD2
Bit6
A FLASHDAT write replaces the data in the FLASHDAT register, but is otherwise
A FLASHDAT write initiates a write of FLASHDAT into the memory address by the
FLASHADR register. FLASHADR is incremented by one when complete.
A FLASHDAT write initiates an erasure (sets all bytes to 0xFF) of the Flash page
containing the address in FLASHADR. The data written must be 0xA5 for the erase
to occur. FLASHADR is not affected. If FLASHADR = 0x1FBFE – 0x1FBFF, the
entire user space will be erased (i.e. entire Flash memory except for Reserved area
0x1FC00 – 0x1FFFF).
A FLASHDAT read provides the data in the FLASHDAT register, but is otherwise
ignored.
A FLASHDAT read initiates a read of the byte addressed by the FLASHADR register
if no operation is currently active. This mode is used for block reads.
A FLASHDAT read initiates a read of the byte addressed by FLASHADR only if no
operation is active and any data from a previous read has already been read from
FLASHDAT. This mode allows single bytes to be read (or the last byte of a block)
without initiating an extra read.
WRMD1
Bit5
WRMD0
Bit4
RDMD3
Rev. 1.4
Bit3
C8051F120/1/2/3/4/5/6/7
RDMD2
Bit2
C8051F130/1/2/3
RDMD1
Bit1
RDMD0
Bit0
00000000
Reset Value
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