C8051F130-GQR Silicon Laboratories Inc, C8051F130-GQR Datasheet - Page 193

• Manufacturer Part Number: C8051F130-GQR
• Description: IC 8051 MCU 128K FLASH 100TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F13xr

Specifications of C8051F130-GQR

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 64
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8.25K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Processor Series: C8051F1x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 8.25 KB
• Interface Type: I2C, SMBus, SPI, UART
• Maximum Clock Frequency: 100 MHz
• Number Of Programmable I/os: 64
• Number Of Timers: 5
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F120DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

To shut down the PLL, the system clock should be switched to the internal oscillator or a stable external
clock source, using the CLKSEL register. Next, disable the PLL by setting PLLEN (PLL0CN.1) to ‘0’.
Finally, the PLL can be powered off, by setting PLLPWR (PLL0CN.0) to ‘0’. Note that the PLLEN and
PLLPWR bits can be cleared at the same time.
Bits 7–5: UNUSED: Read = 000b; Write = don’t care.
Bit 4:
Bit 3:
Bit 2:
Bit 1:
Bit 0:
R/W
Bit7
-
PLLCK: PLL Lock Flag.
0: PLL Frequency is not locked.
1: PLL Frequency is locked.
RESERVED. Must write to ‘0’.
PLLSRC: PLL Reference Clock Source Select Bit.
0: PLL Reference Clock Source is Internal Oscillator.
1: PLL Reference Clock Source is External Oscillator.
PLLEN: PLL Enable Bit.
0: PLL is held in reset.
1: PLL is enabled. PLLPWR must be ‘1’.
PLLPWR: PLL Power Enable.
0: PLL bias generator is de-activated. No static power is consumed.
1: PLL bias generator is active. Must be set for PLL to operate.
page 199
should be disabled whenever the FLRT bits are changed to a lower setting.
R/W
Bit6
-
). Important Note: Cache reads, cache writes, and the prefetch engine
SFR Definition 14.5. PLL0CN: PLL Control
R/W
Bit5
-
PLLLCK
Bit4
R
Rev. 1.4
R/W
Bit3
0
C8051F120/1/2/3/4/5/6/7
PLLSRC
R/W
Bit2
C8051F130/1/2/3
PLLEN
R/W
Bit1
SFR Address:
PLLPWR 00000000
SFR Page:
R/W
Bit0
0x89
F
Reset Value
193