C8051F130-GQR Silicon Laboratories Inc, C8051F130-GQR Datasheet - Page 291

• Manufacturer Part Number: C8051F130-GQR
• Description: IC 8051 MCU 128K FLASH 100TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F13xr

Specifications of C8051F130-GQR

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 64
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8.25K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Processor Series: C8051F1x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 8.25 KB
• Interface Type: I2C, SMBus, SPI, UART
• Maximum Clock Frequency: 100 MHz
• Number Of Programmable I/os: 64
• Number Of Timers: 5
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F120DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

21.1.3. Mode 2: 9-Bit UART, Fixed Baud Rate
Mode 2 provides asynchronous, full-duplex communication using a total of eleven bits per data byte: a start
bit, 8 data bits (LSB first), a programmable ninth data bit, and a stop bit. Mode 2 supports multiprocessor
communications and hardware address recognition (see
determined by the value in TB80 (SCON0.3). It can be assigned the value of the parity flag P in the PSW or
used in multiprocessor communications. On receive, the ninth data bit goes into RB80 (SCON0.2) and the
stop bit is ignored.
Data transmission begins when an instruction writes a data byte to the SBUF0 register. The TI0 Transmit
Interrupt Flag (SCON0.1) is set at the end of the transmission (the beginning of the stop-bit time). Data
reception can begin any time after the REN0 Receive Enable bit (SCON0.4) is set to logic 1. After the stop
bit is received, the data byte will be loaded into the SBUF0 receive register if RI0 is logic 0 and one of the
following requirements are met:
If the above conditions are satisfied, the eight bits of data are stored in SBUF0, the ninth bit is stored in
RB80 and the RI0 flag is set. If these conditions are not met, SBUF0 and RB80 will not be loaded and the
RI0 flag will not be set. An interrupt will occur if enabled when either TI0 or RI0 are set.
The baud rate in Mode 2 is either SYSCLK / 32 or SYSCLK / 64, according to the value of the SMOD0 bit
in register SSTA0.
SPACE
MARK
BIT TIMES
BIT SAMPLING
1. SM20 is logic 0
2. SM20 is logic 1, the received 9th bit is logic 1, and the received address matches the UART0
address as described in
START
BIT
Figure 21.5. UART0 Modes 2 and 3 Timing Diagram
D0
Equation 21.5. Mode 2 Baud Rate
D1
BaudRate
Section 21.2
D2
=
D3
2
Rev. 1.4
.
SMOD0
C8051F120/1/2/3/4/5/6/7
D4
Section 21.2



SYSCLK
--------------------- -
D5
64
C8051F130/1/2/3
). On transmit, the ninth data bit is


D6
D7
D8
STOP
BIT
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