C8051F130-GQR Silicon Laboratories Inc, C8051F130-GQR Datasheet - Page 237

• Manufacturer Part Number: C8051F130-GQR
• Description: IC 8051 MCU 128K FLASH 100TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F13xr

Specifications of C8051F130-GQR

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 64
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8.25K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Processor Series: C8051F1x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 8.25 KB
• Interface Type: I2C, SMBus, SPI, UART
• Maximum Clock Frequency: 100 MHz
• Number Of Programmable I/os: 64
• Number Of Timers: 5
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F120DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

A wide array of digital resources is available through the four lower I/O Ports: P0, P1, P2, and P3. Each of
the pins on P0, P1, P2, and P3, can be defined as a General-Purpose I/O (GPIO) pin or can be controlled
by a digital peripheral or function (like UART0 or /INT1 for example), as shown in Figure 18.2. The system
designer controls which digital functions are assigned pins, limited only by the number of pins available.
This resource assignment flexibility is achieved through the use of a Priority Crossbar Decoder. Note that
the state of a Port I/O pin can always be read from its associated Data register regardless of whether that
pin has been assigned to a digital peripheral or behaves as GPIO. The Port pins on Port 1 can be used as
Analog Inputs to ADC2.
An External Memory Interface which is active during the execution of an off-chip MOVX instruction can be
active on either the lower Ports or the upper Ports. See
and On-Chip XRAM” on page 219
Highest
Priority
Lowest
Priority
Latches
Port
T2, T2EX,
/SYSCLK divided by 1,2,4, or 8
CNVSTR0/2
T4,T4EX
Comptr.
Outputs
UART0
UART1
SMBus
T0, T1,
/INT0,
/INT1
PCA
P0
P1
P2
P3
SPI
(P0.0-P0.7)
(P1.0-P1.7)
(P2.0-P2.7)
(P3.0-P3.7)
8
8
8
8
Figure 18.2. Port I/O Functional Block Diagram
2
4
2
2
7
2
8
2
for more information about the External Memory Interface.
XBR2, P1MDIN
XBR0, XBR1,
Crossbar
Decoder
To External
Registers
Priority
Rev. 1.4
Digital
Interface
Memory
(EMIF)
C8051F120/1/2/3/4/5/6/7
Section “17. External Data Memory Interface
8
8
8
8
P0MDOUT, P1MDOUT,
P2MDOUT, P3MDOUT
Registers
C8051F130/1/2/3
Cells
Cells
Cells
Cells
To ADC2 Input
I/O
I/O
I/O
I/O
P0
P1
P2
P3
(‘F12x Only)
External
Pins
P0.0
P0.7
P1.0
P1.7
P2.0
P2.7
P3.0
P3.7
Highest
Priority
Lowest
Priority
237