C8051F130-GQR Silicon Laboratories Inc, C8051F130-GQR Datasheet - Page 349

• Manufacturer Part Number: C8051F130-GQR
• Description: IC 8051 MCU 128K FLASH 100TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F13xr

Specifications of C8051F130-GQR

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 64
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8.25K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Processor Series: C8051F1x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 8.25 KB
• Interface Type: I2C, SMBus, SPI, UART
• Maximum Clock Frequency: 100 MHz
• Number Of Programmable I/os: 64
• Number Of Timers: 5
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F120DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

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Revision 1.3 to Revision 1.4
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OCUMENT
Added new paragraph tags: SFR Definition and JTAG Register Definition.
Product Selection Guide Table 1.1: Added RoHS-compliant ordering information.
Overview Chapter, Figure 1.8, “On-Chip Memory Map”: Corrected on-chip XRAM size to “8192 Bytes”.
SAR8 Chapter: Table 7.1, “ADC2 Electrical Characteristics”: Track/Hold minimum spec corrected to
“300 ns”.
SAR8 Chapter: Table 7.1, “ADC2 Electrical Characteristics”: Total Harmonic Distortion typical spec
corrected to “-51 dB”.
Oscillators Chapter, Figure 14.1, “Oscillator Diagram”: Corrected location of IOSCEN arrow.
CIP51 Chapter,
cycle instruction.
CIP51 Chapter, Interrupt Summary Table: Added “SFRPAGE” column and SFRPAGE value for each
interrupt source.
CIP-51 Chapter, Figure 11.2, “Memory Map”: Corrected on-chip XRAM size to “8192 Bytes”.
Port I/O Chapter, Crossbar Priority Figures: Character formatting problem corrected.
Port I/O Chapter, P7MDOUT Register Description: Removed references to UART and SMBus periph-
erals.
Port I/O Chapter, P3MDOUT Register Description: Corrected text to read “P3MDOUT.[7:0]”.
Timers Chapter: References to “TnCON” corrected to read “TMRnCN”.
PCA0 Chapter, Section 24.1: Added note about PCA0CN Register and effects of read-modify-write
instructions on the CF bit.
C
Section 11.3
HANGE
L
: Added note describing EA change behavior when followed by single-
IST
Rev. 1.4
C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
349