C8051F130-GQR Silicon Laboratories Inc, C8051F130-GQR Datasheet - Page 92

• Manufacturer Part Number: C8051F130-GQR
• Description: IC 8051 MCU 128K FLASH 100TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F13xr

Specifications of C8051F130-GQR

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 64
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8.25K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Processor Series: C8051F1x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 8.25 KB
• Interface Type: I2C, SMBus, SPI, UART
• Maximum Clock Frequency: 100 MHz
• Number Of Programmable I/os: 64
• Number Of Timers: 5
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F120DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
7.2.
ADC2 has a maximum conversion speed of 500 ksps. The ADC2 conversion clock (SAR2 clock) is a
divided version of the system clock, determined by the AD2SC bits in the ADC2CF register. The maximum
ADC2 conversion clock is 6 MHz.
7.2.1. Starting a Conversion
A conversion can be initiated in one of five ways, depending on the programmed states of the ADC2 Start
of Conversion Mode bits (AD2CM2-0) in ADC2CN. Conversions may be initiated by:
During conversion, the AD2BUSY bit is set to logic 1 and restored to 0 when conversion is complete. The
falling edge of AD2BUSY triggers an interrupt (when enabled) and sets the interrupt flag in ADC2CN. Con-
verted data is available in the ADC2 data word, ADC2.
When a conversion is initiated by writing a ‘1’ to AD2BUSY, it is recommended to poll AD2INT to determine
when the conversion is complete. The recommended procedure is:
When CNVSTR2 is used as a conversion start source, it must be enabled in the crossbar, and the corre-
sponding pin must be set to open-drain, high-impedance mode (see
page 235
7.2.2. Tracking Modes
The AD2TM bit in register ADC2CN controls the ADC2 track-and-hold mode. In its default state, the ADC2
input is continuously tracked, except when a conversion is in progress. When the AD2TM bit is logic 1,
ADC2 operates in low-power track-and-hold mode. In this mode, each conversion is preceded by a track-
ing period of 3 SAR clocks (after the start-of-conversion signal). When the CNVSTR2 signal is used to ini-
tiate conversions in low-power tracking mode, ADC2 tracks only when CNVSTR2 is low; conversion
begins on the rising edge of CNVSTR2 (see Figure 7.2). Tracking can also be disabled (shutdown) when
the entire chip is in low power standby or sleep modes. Low-power Track-and-Hold mode is also useful
when AMUX or PGA settings are frequently changed, due to the settling time requirements described in
Section “7.2.3. Settling Time Requirements” on page 94
92
ADC2 Modes of Operation
1. Writing a ‘1’ to the AD2BUSY bit of ADC2CN;
2. A Timer 3 overflow (i.e. timed continuous conversions);
3. A rising edge detected on the external ADC convert start signal, CNVSTR2;
4. A Timer 2 overflow (i.e. timed continuous conversions);
5. Writing a ‘1’ to the AD0BUSY of register ADC0CN (initiate conversion of ADC2 and ADC0 with
Step 1. Write a ‘0’ to AD2INT;
Step 2. Write a ‘1’ to AD2BUSY;
Step 3. Poll AD2INT for ‘1’;
Step 4. Process ADC2 data.
for more details on Port I/O configuration).
a single software command).
Rev. 1.4
.
Section “18. Port Input/Output” on