C8051F130-GQR Silicon Laboratories Inc, C8051F130-GQR Datasheet - Page 250

• Manufacturer Part Number: C8051F130-GQR
• Description: IC 8051 MCU 128K FLASH 100TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F13xr

Specifications of C8051F130-GQR

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 64
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8.25K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Processor Series: C8051F1x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 8.25 KB
• Interface Type: I2C, SMBus, SPI, UART
• Maximum Clock Frequency: 100 MHz
• Number Of Programmable I/os: 64
• Number Of Timers: 5
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F120DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
250
Bits7–0: P1MDOUT.[7:0]: Port1 Output Mode Bits.
Bits7–0: P2.[7:0]: Port2 Output Latch Bits.
Note:
Note:
P2.7
R/W
R/W
Bit7
Bit7
(Write - Output appears on I/O pins per XBR0, XBR1, and XBR2 Registers)
0: Logic Low Output.
1: Logic High Output (open if corresponding P2MDOUT.n bit = 0).
(Read - Regardless of XBR0, XBR1, and XBR2 Register settings).
0: P2.n pin is logic low.
1: P2.n pin is logic high.
P2.[7:0] can be driven by the External Data Memory Interface (as Address[15:8] in Multiplexed
mode, or as Address[7:0] in Non-multiplexed mode). See
Memory Interface and On-Chip XRAM” on page 219
External Memory Interface.
0: Port Pin output mode is configured as Open-Drain.
1: Port Pin output mode is configured as Push-Pull.
SDA, SCL, and RX0 (when UART0 is in Mode 0) and RX1 (when UART1 is in Mode 0) are
always configured as Open-Drain when they appear on Port pins.
P2.6
R/W
R/W
Bit6
Bit6
SFR Definition 18.8. P1MDOUT: Port1 Output Mode
P2.5
R/W
R/W
Bit5
Bit5
SFR Definition 18.9. P2: Port2 Data
P2.4
R/W
R/W
Bit4
Bit4
Rev. 1.4
P2.3
R/W
R/W
Bit3
Bit3
P2.2
R/W
R/W
Bit2
Bit2
for more information about the
Section “17. External Data
P2.1
R/W
R/W
Bit1
Bit1
SFR Address:
SFR Page:
SFR Page:
P2.0
R/W
Address:
R/W
Bit0
Bit0
SFR
0xA5
F
0xA0
All Pages
Addressable
00000000
Reset Value
Reset Value
11111111
Bit