C8051F130-GQR Silicon Laboratories Inc, C8051F130-GQR Datasheet - Page 205

• Manufacturer Part Number: C8051F130-GQR
• Description: IC 8051 MCU 128K FLASH 100TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F13xr

Specifications of C8051F130-GQR

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 64
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8.25K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Processor Series: C8051F1x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 8.25 KB
• Interface Type: I2C, SMBus, SPI, UART
• Maximum Clock Frequency: 100 MHz
• Number Of Programmable I/os: 64
• Number Of Timers: 5
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F120DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Flash Read Lock Byte
Bits7–0: Each bit locks a corresponding block of memory. (Bit7 is MSB).
Flash Write/Erase Lock Byte
Bits7–0: Each bit locks a corresponding block of memory.
Flash access Limit Register (FLACL)
Read and Write/Erase Security Bits.
(Bit 7 is MSB.)
Bit
7
6
5
4
3
2
1
0
0x0C000 - 0x0FFFF
0x08000 - 0x0BFFF
0x04000 - 0x07FFF
0x00000 - 0x03FFF
Memory Block
0: Read operations are locked (disabled) for corresponding block across the JTAG interface.
1: Read operations are unlocked (enabled) for corresponding block across the JTAG inter-
face.
0: Write/Erase operations are locked (disabled) for corresponding block across the JTAG
interface.
1: Write/Erase operations are unlocked (enabled) for corresponding block across the JTAG
interface.
NOTE: When the highest block is locked, the security bytes may be written but not erased.
The Flash Access Limit is defined by the setting of the FLACL register, as described in SFR
Definition 15.1. Firmware running at or above this address is prohibited from using the
MOVX and MOVC instructions to read, write, or erase Flash locations below this address.
Figure 15.3. 64 kB Flash Memory Map and Security Bytes
N/A
N/A
N/A
N/A
Write/Erase Lock Byte
Read Lock Byte
Memory Space
Program/Data
SFLE = 0
Rev. 1.4
C8051F120/1/2/3/4/5/6/7
0x0FFFF
0x0FFFE
0x0FFFD
0x00000
Flash Access Limit
C8051F130/1/2/3
Scratchpad Memory
SFLE = 1
(Data only)
0x00FF
0x0000
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