PIC17LC752T-08I/L Microchip Technology, PIC17LC752T-08I/L Datasheet - Page 103

• Manufacturer Part Number: PIC17LC752T-08I/L
• Description: IC MCU OTP 8KX16 A/D 68PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 17Cr

Specifications of PIC17LC752T-08I/L

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: OTP
• Ram Size: 678 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 68-PLCC
• Processor Series: PIC17LC
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 678 B
• Interface Type: I2C, MSSP, RS- 232, SCI, SPI, USART
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 50
• Number Of Timers: 8
• Operating Supply Voltage: 3 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ICE2000, DM173001
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

REGISTER 13-3: TCON3 REGISTER (ADDRESS: 16h, BANK 7)
2000 Microchip Technology Inc.
bit 7
bit 6
bit 5
bit 4-3
bit 2-1
bit 0
Legend:
R = Readable bit
- n = Value at POR Reset
bit 7
Unimplemented: Read as ‘0’
CA4OVF: Capture4 Overflow Status bit
This bit indicates that the capture value had not been read from the capture register pair
(CA4H:CA4L) before the next capture event occurred. The capture register retains the oldest
unread capture value (last capture before overflow). Subsequent capture events will not update
the capture register with the TMR3 value until the capture register has been read (both bytes).
1 = Overflow occurred on Capture4 registers
0 = No overflow occurred on Capture4 registers
CA3OVF: Capture3 Overflow Status bit
This bit indicates that the capture value had not been read from the capture register pair
(CA3H:CA3L) before the next capture event occurred. The capture register retains the oldest
unread capture value (last capture before overflow). Subsequent capture events will not update
the capture register with the TMR3 value until the capture register has been read (both bytes).
1 = Overflow occurred on Capture3 registers
0 = No overflow occurred on Capture3 registers
CA4ED1:CA4ED0: Capture4 Mode Select bits
00 = Capture on every falling edge
01 = Capture on every rising edge
10 = Capture on every 4th rising edge
11 = Capture on every 16th rising edge
CA3ED1:CA3ED0: Capture3 Mode Select bits
00 = Capture on every falling edge
01 = Capture on every rising edge
10 = Capture on every 4th rising edge
11 = Capture on every 16th rising edge
PWM3ON: PWM3 On bit
1 = PWM3 is enabled (the RG5/PWM3 pin ignores the state of the DDRG<5> bit)
0 = PWM3 is disabled (the RG5/PWM3 pin uses the state of the DDRG<5> bit for data direction)
U-0
—
CA4OVF
R-0
CA3OVF
R-0
W = Writable bit
’1’ = Bit is set
CA4ED1
R/W-0
CA4ED0
R/W-0
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
CA3ED1
R/W-0
PIC17C7XX
x = Bit is unknown
CA3ED0 PWM3ON
R/W-0
DS30289B-page 103
R/W-0
bit 0