PIC17LC752T-08I/L Microchip Technology, PIC17LC752T-08I/L Datasheet - Page 113

• Manufacturer Part Number: PIC17LC752T-08I/L
• Description: IC MCU OTP 8KX16 A/D 68PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 17Cr

Specifications of PIC17LC752T-08I/L

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: OTP
• Ram Size: 678 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 68-PLCC
• Processor Series: PIC17LC
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 678 B
• Interface Type: I2C, MSSP, RS- 232, SCI, SPI, USART
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 50
• Number Of Timers: 8
• Operating Supply Voltage: 3 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ICE2000, DM173001
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

13.2.3
The Capture overflow status flag bits are double buff-
ered. The master bit is set if one captured word is
already residing in the Capture register and another
“event” has occurred on the CAPx pin. The new event
will not transfer the TMR3 value to the capture register,
protecting the previous unread capture value. When
the user reads both the high and the low bytes (in any
EXAMPLE 13-1:
TABLE 13-6:
16h, Bank 3
17h, Bank 3
16h, Bank 7
12h, Bank 2
13h, Bank 2
16h, Bank 1
17h, Bank 1
10h, Bank 4
11h, Bank 4
07h, Unbanked INTSTA
06h, Unbanked CPUSTA
16h, Bank 2
17h, Bank 2
14h, Bank 3
15h, Bank 3
12h, Bank 7
13h, Bank 7
14h, Bank 7
15h, Bank 7
Legend:
2000 Microchip Technology Inc.
Address
MOVLB 3
MOVPF CA2L, LO_BYTE
MOVPF CA2H, HI_BYTE
MOVPF TCON2, STAT_VAL
x = unknown, u = unchanged, - = unimplemented, read as '0', q = value depends on condition.
Shaded cells are not used by Capture.
READING THE CAPTURE
REGISTERS
TCON1
TCON2
TCON3
TMR3L
TMR3H
PIR1
PIE1
PIR2
PIE2
PR3L/CA1L
PR3H/CA1H Timer3 Period Register, High Byte/Capture1 Register, High Byte
CA2L
CA2H
CA3L
CA3H
CA4L
CA4H
Name
REGISTERS ASSOCIATED WITH CAPTURE
SEQUENCE TO READ CAPTURE REGISTERS
Holding Register for the Low Byte of the 16-bit TMR3 Register
Holding Register for the High Byte of the 16-bit TMR3 Register
Timer3 Period Register, Low Byte/Capture1 Register, Low Byte
Capture2 Low Byte
Capture2 High Byte
Capture3 Low Byte
Capture3 High Byte
Capture4 Low Byte
Capture4 High Byte
CA2ED1 CA2ED0
CA2OVF CA1OVF PWM2ON
SSPIF
SSPIE
RBIE
Bit 7
RBIF
PEIF
—
—
CA4OVF
TMR3IF
TMR3IE
T0CKIF
BCLIF
BCLIE
Bit 6
—
; Select Bank 3
; Read Capture2 low byte, store in LO_BYTE
; Read Capture2 high byte, store in HI_BYTE
; Read TCON2 into file STAT_VAL
CA3OVF
CA1ED1
TMR2IF
TMR2IE
STKAV
ADIF
ADIE
Bit 5
T0IF
PWM1ON CA1/PR3 TMR3ON TMR2ON TMR1ON 0000 0000
CA1ED0
CA4ED1
TMR1IF
TMR1IE
GLINTD
Bit 4
INTF
—
—
CA4ED0 CA3ED1
CA2IE
CA4IE
CA2IF
CA4IF
order) of the Capture register, the master overflow bit is
transferred to the slave overflow bit (CAxOVF) and
then the master bit is reset. The user can then read
TCONx to determine the value of CAxOVF.
An example of an instruction sequence to read capture
registers and capture overflow flag bits is shown in
Example 13-1. Depending on the capture source, dif-
ferent registers will need to be read.
PEIE
Bit 3
T16
TO
TMR3CS TMR2CS TMR1CS 0000 0000
T0CKIE
CA1IE
CA3IE
CA1IF
CA3IF
Bit 2
PD
CA3ED0 PWM3ON -000 0000
TX1IE
TX2IE
TX1IF
TX2IF
Bit 1
T0IE
POR
PIC17C7XX
RC1IF
RC1IE
RC2IF
RC2IE
INTE
Bit 0
BOR
xxxx xxxx
xxxx xxxx
x000 0010
0000 0000
000- 0010
000- 0000
0000 0000
--11 11qq
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
Value on
DS30289B-page 113
POR,
BOR
MCLR, WDT
0000 0000
0000 0000
-000 0000
uuuu uuuu
uuuu uuuu
u000 0010
0000 0000
000- 0010
000- 0000
0000 0000
--11 qquu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu