PIC17LC752T-08I/L Microchip Technology, PIC17LC752T-08I/L Datasheet - Page 75

• Manufacturer Part Number: PIC17LC752T-08I/L
• Description: IC MCU OTP 8KX16 A/D 68PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 17Cr

Specifications of PIC17LC752T-08I/L

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: OTP
• Ram Size: 678 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 68-PLCC
• Processor Series: PIC17LC
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 678 B
• Interface Type: I2C, MSSP, RS- 232, SCI, SPI, USART
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 50
• Number Of Timers: 8
• Operating Supply Voltage: 3 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ICE2000, DM173001
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Example 10-2 shows an instruction sequence to initial-
ize PORTB. The Bank Select Register (BSR) must be
selected to Bank 0 for the port to be initialized. The fol-
lowing example uses the MOVLB instruction to load the
BSR register for bank selection.
FIGURE 10-6:
2000 Microchip Technology Inc.
Note: I/O pins have protection diodes to V
Weak
Pull-up
OE
BLOCK DIAGRAM OF RB3:RB2 PORT PINS
DD
and V
SS
Port
Input Latch
.
Port
Data
Q
EXAMPLE 10-2:
MOVLB
CLRF
MOVLW
MOVWF
CK
D
PORTB, F
0xCF
DDRB
0
Match Signal
from other
port pins
Q
; Init PORTB by clearing
;
; Value used to initialize
;
; Set RB<3:0> as inputs
;
;
; Select Bank 0
R
INITIALIZING PORTB
PIC17C7XX
output data latches
data direction
CK
RB<5:4> as outputs
RB<7:6> as inputs
D
RBPU
Peripheral Data In
DS30289B-page 75
Peripheral_enable
WR_PORTB (Q4)
Peripheral_output
RD_PORTB (Q2)
WR_DDRB (Q4)
RD_DDRB (Q2)
(PORTA<7>)
Data Bus
RBIF