PIC17LC752T-08I/L Microchip Technology, PIC17LC752T-08I/L Datasheet - Page 61

• Manufacturer Part Number: PIC17LC752T-08I/L
• Description: IC MCU OTP 8KX16 A/D 68PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 17Cr

Specifications of PIC17LC752T-08I/L

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: OTP
• Ram Size: 678 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 68-PLCC
• Processor Series: PIC17LC
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 678 B
• Interface Type: I2C, MSSP, RS- 232, SCI, SPI, USART
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 50
• Number Of Timers: 8
• Operating Supply Voltage: 3 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ICE2000, DM173001
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

8.1
A table write operation to internal memory causes a
long write operation. The long write is necessary for
programming the internal EPROM. Instruction execu-
tion is halted while in a long write cycle. The long write
will be terminated by any enabled interrupt. To ensure
that the EPROM location has been well programmed,
a minimum programming time is required (see specifi-
cation #D114). Having only one interrupt enabled to ter-
minate the long write ensures that no unintentional
interrupts will prematurely terminate the long write.
The sequence of events for programming an internal
program memory location should be:
1.
2.
3.
4.
5.
TABLE 8-1:
RA0/INT,
TMR0,
T0CKI
Peripheral
2000 Microchip Technology Inc.
Note 1: Programming requirements must be
Disable all interrupt sources, except the source
to terminate EPROM program write.
Raise MCLR/V
voltage.
Clear the WDT.
Do the table write. The interrupt will terminate
the long write.
Verify the memory location (table read).
Interrupt
Source
Table Writes to Internal Memory
2: If the V
met. See timing specification in electrical
specifications for the desired device.
Violating these specifications (including
temperature) may result in EPROM
locations that are not fully programmed
and may lose their state over time.
table write is a 2-cycle write and the pro-
gram memory is unchanged.
INTERRUPT - TABLE WRITE INTERACTION
PP
PP
GLINTD
requirement is not met, the
pin to the programming
0
0
1
1
0
0
1
1
Enable
Bit
1
1
0
1
1
1
0
1
Flag
Bit
1
0
x
1
1
0
x
1
Terminate long table write (to internal program memory),
branch to interrupt vector (branch clears flag bit).
None.
None.
Terminate long table write, do not branch to interrupt
vector (flag is automatically cleared).
Terminate long table write, branch to interrupt vector.
None.
None.
Terminate long table write, do not branch to interrupt
vector (flag remains set).
8.1.1
An interrupt source or RESET are the only events that
terminate a long write operation. Terminating the long
write from an interrupt source requires that the interrupt
enable and flag bits are set. The GLINTD bit only
enables the vectoring to the interrupt address.
If the T0CKI, RA0/INT, or TMR0 interrupt source is
used to terminate the long write, the interrupt flag of the
highest priority enabled interrupt, will terminate the long
write and automatically be cleared.
If a peripheral interrupt source is used to terminate the
long write, the interrupt enable and flag bits must be
set. The interrupt flag will not be automatically cleared
upon the vectoring to the interrupt vector address.
The GLINTD bit determines whether the program will
branch to the interrupt vector when the long write is ter-
minated. If GLINTD is clear, the program will vector, if
GLINTD is set, the program will not vector to the
interrupt address.
Note 1: If an interrupt is pending, the TABLWT is
2: If the interrupt is not being used for the
TERMINATING LONG WRITES
aborted (a NOP is executed). The highest
priority pending interrupt, from the
T0CKI, RA0/INT, or TMR0 sources that
is enabled, has its flag cleared.
program write timing, the interrupt
should be disabled. This will ensure that
the interrupt is not lost, nor will it termi-
nate the long write prematurely.
Action
PIC17C7XX
DS30289B-page 61