PIC17LC752T-08I/L Microchip Technology, PIC17LC752T-08I/L Datasheet - Page 109

• Manufacturer Part Number: PIC17LC752T-08I/L
• Description: IC MCU OTP 8KX16 A/D 68PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 17Cr

Specifications of PIC17LC752T-08I/L

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: OTP
• Ram Size: 678 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 68-PLCC
• Processor Series: PIC17LC
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 678 B
• Interface Type: I2C, MSSP, RS- 232, SCI, SPI, USART
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 50
• Number Of Timers: 8
• Operating Supply Voltage: 3 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ICE2000, DM173001
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

13.1.3.3
The PWMs will operate, regardless of the clock source
of the timer. The use of an external clock has ramifica-
tions that must be understood. Because the external
TCLK12 input is synchronized internally (sampled once
per instruction cycle), the time TCLK12 changes to the
time the timer increments, will vary by as much as 1T
(one instruction cycle). This will cause jitter in the duty
cycle as well as the period of the PWM output.
This jitter will be 1T
chronized with the processor clock. Use of one of the
PWM outputs as the clock source to the TCLK12 input,
will supply a synchronized clock.
In general, when using an external clock source for
PWM, its frequency should be much less than the
device frequency (F
TABLE 13-5:
16h, Bank 3
17h, Bank 3
16h, Bank 7
10h, Bank 2
11h, Bank 2
16h, Bank 1
17h, Bank 1
07h, Unbanked INTSTA
06h, Unbanked CPUSTA
14h, Bank 2
15h, Bank 2
10h, Bank 3
11h, Bank 3
10h, Bank 7
12h, Bank 3
13h, Bank 3
11h, Bank 7
Legend:
2000 Microchip Technology Inc.
Address
x = unknown, u = unchanged, - = unimplemented, read as '0', q = value depends on conditions.
Shaded cells are not used by PWM Module.
External Clock Source
TCON1
TCON2
TCON3
TMR1
TMR2
PIR1
PIE1
PR1
PR2
PW1DCL
PW2DCL
PW3DCL
PW1DCH
PW2DCH
PW3DCH
Name
REGISTERS/BITS ASSOCIATED WITH PWM
CY
OSC
, unless the external clock is syn-
).
Timer1’s Register
Timer2’s Register
Timer1 Period Register
Timer2 Period Register
CA2ED1
CA2OVF
RBIE
Bit 7
RBIF
PEIF
DC1
DC1
DC1
DC9
DC9
DC9
—
—
CA2ED0
CA1OVF
CA4OVF
TMR3IF
TMR3IE
T0CKIF
Bit 6
DC0
DC0
DC0
DC8
DC8
DC8
—
PWM2ON PWM1ON CA1/PR3 TMR3ON TMR2ON
TM2PW2
TM2PW3
CA3OVF
CA1ED1
TMR2IF
TMR2IE
STKAV
Bit 5
T0IF
DC7
DC7
DC7
—
CY
CA1ED0
CA4ED1
TMR1IE
GLINTD
TMR1IF
Bit 4
INTF
DC6
DC6
DC6
—
—
—
CA4ED0
13.1.3.4
The use of an external clock for the PWM time base
(Timer1 or Timer2) limits the PWM output to a maxi-
mum resolution of 8-bits. The PWxDCL<7:6> bits must
be kept cleared. Use of any other value will distort the
PWM output. All resolutions are supported when inter-
nal clock mode is selected. The maximum attainable
frequency is also lower. This is a result of the timing
requirements of an external clock input for a timer (see
the Electrical Specification section). The maximum
PWM frequency, when the timers clock source is the
RB4/TCLK12 pin, is shown in Table 13-4 (Standard
Resolution mode).
CA2IF
CA2IE
PEIE
Bit 3
DC5
DC5
DC5
T16
TO
—
—
—
TMR3CS
CA3ED1
T0CKIE
CA1IE
CA1IF
Bit 2
DC4
DC4
DC4
PD
—
—
—
Maximum Resolution/Frequency for
External Clock Input
TMR2CS
CA3ED0
TX1IE
TX1IF
Bit 1
T0IE
POR
DC3
DC3
DC3
—
—
—
PIC17C7XX
PWM3ON
TMR1ON
TMR1CS
RC1IE
RC1IF
INTE
Bit 0
BOR
DC2
DC2
DC2
—
—
—
DS30289B-page 109
0000 0000 0000 0000
0000 0000 0000 0000
-000 0000 -000 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
x000 0010 u000 0010
0000 0000 0000 0000
0000 0000 0000 0000
--11 11qq --11 qquu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xx-- ---- uu-- ----
xx0- ---- uu0- ----
xx0- ---- uu0- ----
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
Value on
POR,
BOR
MCLR,
WDT