PIC17LC752T-08I/L Microchip Technology, PIC17LC752T-08I/L Datasheet - Page 215

• Manufacturer Part Number: PIC17LC752T-08I/L
• Description: IC MCU OTP 8KX16 A/D 68PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 17Cr

Specifications of PIC17LC752T-08I/L

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: OTP
• Ram Size: 678 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 68-PLCC
• Processor Series: PIC17LC
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 678 B
• Interface Type: I2C, MSSP, RS- 232, SCI, SPI, USART
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 50
• Number Of Timers: 8
• Operating Supply Voltage: 3 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ICE2000, DM173001
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

IORWF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example:
2000 Microchip Technology Inc.
Before Instruction
After Instruction
Decode
RESULT =
WREG
RESULT =
WREG
Q1
=
=
register ’f’
Inclusive OR WREG with f
[ label ]
0
d
(WREG) .OR. (f)
Z
Inclusive OR WREG with register ’f’. If
’d’ is 0, the result is placed in WREG. If
’d’ is 1, the result is placed back in
register ’f’.
1
1
IORWF
Read
0000
Q2
0x13
0x91
0x13
0x93
f
[0,1]
255
RESULT, 0
IORWF
100d
Process
Data
Q3
ffff
f,d
(dest)
destination
Write to
Q4
ffff
LCALL
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example:
Before Instruction
After Instruction
operation
Decode
SUBROUTINE =
PC
PC
Q1
No
operation
Long Call
[ label ]
0
PC + 1
k
None
LCALL allows an unconditional subrou-
tine call to anywhere within the 64K
program memory space.
First, the return address (PC + 1) is
pushed onto the stack. A 16-bit desti-
nation address is then loaded into the
program counter. The lower 8-bits of
the destination address are embedded
in the instruction. The upper 8-bits of
PC are loaded from PC high holding
latch, PCLATH.
1
2
MOVLW
MOVPF
LCALL
literal ’k’
Read
1011
Q2
No
=
=
k
PCL, (PCLATH)
PIC17C7XX
255
16-bit Address
?
Address (SUBROUTINE)
HIGH(SUBROUTINE)
WREG, PCLATH
LOW(SUBROUTINE)
LCALL
TOS;
0111
operation
Process
Data
Q3
No
DS30289B-page 215
k
kkkk
register PCL
PCH
operation
Write
Q4
No
kkkk