PIC17LC752T-08I/L Microchip Technology, PIC17LC752T-08I/L Datasheet - Page 126

• Manufacturer Part Number: PIC17LC752T-08I/L
• Description: IC MCU OTP 8KX16 A/D 68PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 17Cr

Specifications of PIC17LC752T-08I/L

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: OTP
• Ram Size: 678 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 68-PLCC
• Processor Series: PIC17LC
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 678 B
• Interface Type: I2C, MSSP, RS- 232, SCI, SPI, USART
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 50
• Number Of Timers: 8
• Operating Supply Voltage: 3 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ICE2000, DM173001
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC17C7XX
Steps to follow when setting up an Asynchronous
Reception:
1.
2.
3.
4.
5.
6.
FIGURE 14-7:
TABLE 14-7:
DS30289B-page 126
16h, Bank 1
17h, Bank 1
13h, Bank 0
14h, Bank 0
15h, Bank 0
17h, Bank 0
10h, Bank 4
11h, Bank 4
13h, Bank 4
14h, Bank 4
15h, Bank 4
17h, Bank 4
Legend:
Address
Rcv Buffer Reg
Initialize the SPBRG register for the appropriate
baud rate.
Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
If interrupts are desired, then set the RCIE bit.
If 9-bit reception is desired, then set the RX9 bit.
Enable the reception by setting the CREN bit.
The RCIF bit will be set when reception com-
pletes and an interrupt will be generated if the
RCIE bit was set.
(Interrupt Flag)
(RX/DT pin)
Buffer Reg
Read Rcv
OERR bit
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
Rcv Shift
RCREG
Reg
x = unknown, u = unchanged, - = unimplemented, read as a '0'. Shaded cells are not used for asynchronous reception.
CREN
RCIF
PIR1
PIE1
RCSTA1
RCREG1
TXSTA1
SPBRG1
PIR2
PIE2
RCSTA2
RCREG2
TXSTA2
SPBRG2
RX
causing the OERR (overrun) bit to be set.
Name
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
START
ASYNCHRONOUS RECEPTION
bit
Baud Rate Generator Register
Baud Rate Generator Register
SSPIE
SPEN
CSRC
SSPIF
SPEN
CSRC
RBIF
RBIE
Bit 7
RX7
RX7
bit0
TMR3IF TMR2IF TMR1IF
TMR3IE TMR2IE TMR1IE
BCLIE
BCLIF
bit1
Bit 6
RX9
RX6
TX9
RX9
RX6
TX9
SREN
TXEN
SREN
TXEN
ADIE
Bit 5
ADIF
RX5
RX5
bit7/8
CREN
SYNC
CREN
SYNC
Bit 4
STOP
RX4
RX4
—
—
bit
Word 1
RCREG
START
CA2IF
CA2IE
CA4IF
CA4IE
bit
Bit 3
RX3
RX3
—
—
—
—
bit0
7.
8.
9.
CA1IF
CA1IE
CA3IF
CA3IE
FERR
FERR
Note:
Bit 2
RX2
RX2
—
—
Read RCSTA to get the ninth bit (if enabled) and
FERR bit to determine if any error occurred dur-
ing reception.
Read RCREG for the 8-bit received data.
If an overrun error occurred, clear the error by
clearing the OERR bit.
bit7/8 STOP
OERR
OERR
To terminate a reception, either clear the
SREN and CREN bits, or the SPEN bit.
This will reset the receive logic, so that it
will be in the proper state when receive is
re-enabled.
TX1IF
TX1IE
TRMT
TX2IF
TX2IE
TRMT
Bit 1
RX1
RX1
bit
RC1IE
RC2IE
Word 2
RCREG
RC1IF
RC2IF
RX9D
RX9D
TX9D
TX9D
Bit 0
RX0
RX0
START
bit
2000 Microchip Technology Inc.
x000 0010
0000 0000
0000 -00x
xxxx xxxx
0000 --1x
0000 0000
000- 0010
000- 0000
0000 -00x
xxxx xxxx
0000 --1x
0000 0000
Value on
POR,
BOR
bit7/8
STOP
Word 3
bit
MCLR, WDT
u000 0010
0000 0000
0000 -00u
uuuu uuuu
0000 --1u
0000 0000
000- 0010
000- 0000
0000 -00u
uuuu uuuu
0000 --1u
0000 0000