PIC17LC752T-08I/L Microchip Technology, PIC17LC752T-08I/L Datasheet - Page 193

• Manufacturer Part Number: PIC17LC752T-08I/L
• Description: IC MCU OTP 8KX16 A/D 68PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 17Cr

Specifications of PIC17LC752T-08I/L

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: OTP
• Ram Size: 678 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 68-PLCC
• Processor Series: PIC17LC
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 678 B
• Interface Type: I2C, MSSP, RS- 232, SCI, SPI, USART
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 50
• Number Of Timers: 8
• Operating Supply Voltage: 3 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ICE2000, DM173001
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

17.3
The Watchdog Timer’s function is to recover from soft-
ware malfunction, or to reset the device while in SLEEP
mode. The WDT uses an internal free running on-chip
RC oscillator for its clock source. This does not require
any external components. This RC oscillator is sepa-
rate from the RC oscillator of the OSC1/CLKIN pin.
That means that the WDT will run even if the clock on
the OSC1/CLKIN and OSC2/CLKOUT pins has been
stopped, for example, by execution of a SLEEP instruc-
tion. During normal operation, a WDT time-out gener-
ates a device RESET. The WDT can be permanently
disabled by programming the configuration bits
WDTPS1:WDTPS0 as '00' (Section 17.1).
Under normal operation, the WDT must be cleared on
a regular interval. This time must be less than the min-
imum WDT overflow time. Not clearing the WDT in this
time frame will cause the WDT to overflow and reset
the device.
17.3.1
The WDT has a nominal time-out period of 12 ms (with
postscaler = 1). The time-out periods vary with temper-
ature, V
DC specs). If longer time-out periods are desired, con-
figuration bits should be used to enable the WDT with
a greater prescale. Thus, typical time-out periods up to
3.0 seconds can be realized.
The CLRWDT and SLEEP instructions clear the WDT
and its postscale setting and prevent it from timing out,
thus generating a device RESET condition.
The TO bit in the CPUSTA register will be cleared upon
a WDT time-out.
FIGURE 17-1:
TABLE 17-2:
Legend:
Note
06h, Unbanked CPUSTA
Note 1: This oscillator is separate from the external
2000 Microchip Technology Inc.
Address
—
1:
DD
Watchdog Timer (WDT)
- = unimplemented, read as '0', q = value depends on condition. Shaded cells are not used by the WDT.
and process variations from part to part (see
This value will be as the device was programmed, or if unprogrammed, will read as all '1's.
RC oscillator on the OSC1 pin.
On-chip RC
WDT PERIOD
Oscillator
Config
Name
REGISTERS/BITS ASSOCIATED WITH THE WATCHDOG TIMER
(1)
WATCHDOG TIMER BLOCK DIAGRAM
See Figure 17-1 for location of WDTPSx bits in Configuration Word.
Bit 7
—
WDT Enable
WDT
Bit 6
—
STKAV
Bit 5
GLINTD
Bit 4
Bit 3
TO
17.3.2
The WDT and postscaler are cleared when:
• The device is in the RESET state
• A SLEEP instruction is executed
• A CLRWDT instruction is executed
• Wake-up from SLEEP by an interrupt
The WDT counter/postscaler will start counting on the
first edge after the device exits the RESET state.
17.3.3
It should also be taken in account that under worst case
conditions (V
WDT postscaler), it may take several seconds before a
WDT time-out occurs.
The WDT and postscaler become the Power-up Timer
whenever the PWRT is invoked.
17.3.4
When the WDT is selected as a normal timer, the clock
source is the device clock. Neither the WDT nor the
postscaler are directly readable or writable. The over-
flow time is 65536 T
is cleared (device is not RESET). The CLRWDT instruc-
tion can be used to set the TO bit. This allows the WDT
to be a simple overflow timer. The simple timer does
not increment when in SLEEP.
Bit 2
PD
4 - to - 1 MUX
WDT Overflow
Postscaler
CLEARING THE WDT AND
POSTSCALER
WDT PROGRAMMING
CONSIDERATIONS
WDT AS NORMAL TIMER
DD
Bit 1
POR
= Min., Temperature = Max., Max.
OSC
cycles. On overflow, the TO bit
Bit 0
BOR
PIC17C7XX
WDTPS1:WDTPS0
--11 11qq
POR, BOR
Value on
(Note 1)
DS30289B-page 193
MCLR, WDT
--11 qquu
(Note 1)