PIC17LC752T-08I/L Microchip Technology, PIC17LC752T-08I/L Datasheet - Page 133

• Manufacturer Part Number: PIC17LC752T-08I/L
• Description: IC MCU OTP 8KX16 A/D 68PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 17Cr

Specifications of PIC17LC752T-08I/L

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: OTP
• Ram Size: 678 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 68-PLCC
• Processor Series: PIC17LC
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 678 B
• Interface Type: I2C, MSSP, RS- 232, SCI, SPI, USART
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 50
• Number Of Timers: 8
• Operating Supply Voltage: 3 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ICE2000, DM173001
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

15.0
The Master Synchronous Serial Port (MSSP) module is
a serial interface useful for communicating with other
peripheral or microcontroller devices. These peripheral
devices may be serial EEPROMs, shift registers, dis-
play drivers, A/D converters, etc. The MSSP module
can operate in one of two modes:
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit
Figure 15-1 shows a block diagram for the SPI mode,
while Figure 15-2 and Figure 15-3 show the block
diagrams for the two different I
FIGURE 15-1:
2000 Microchip Technology Inc.
SDO
SCK
SDI
SS
MASTER SYNCHRONOUS
SERIAL PORT (MSSP)
MODULE
Read
SS Control
SMP:CKE
Select
Edge
Enable
bit0
Select
Edge
SSPBUF reg
SPI MODE BLOCK
DIAGRAM
Data to TX/RX in SSPSR
Data Direction bit
2
SSPSR reg
TM
SSPM3:SSPM0
Clock Select
(I
4
2
C)
2
C modes of operation.
2
Write
Prescaler
4, 16, 64
Clock
Shift
TMR2 Output
Data Bus
Internal
2
Tosc
FIGURE 15-2:
FIGURE 15-3:
SDA
SCL
SDA
SCL
Baud Rate Generator
SSPADD<6:0>
7
Read
Read
Clock
Clock
Shift
Shift
START and STOP bit
MSb
MSb
Detect/Generate
STOP bit Detect
I
DIAGRAM
I
BLOCK DIAGRAM
2
Match Detect
2
SSPADD reg
SSPADD reg
SSPBUF reg
SSPBUF reg
Match detect
START and
SSPSR reg
SSPSR reg
PIC17C7XX
C SLAVE MODE BLOCK
C MASTER MODE
LSb
LSb
DS30289B-page 133
Write
Write
(SSPSTAT reg)
(SSPSTAT reg)
Clear/Set P, bit
and Set SSPIF
Set/Clear S bit
Data Bus
Data Bus
Internal
Internal
Call Detected
Call Detected
Set, Reset
S, P bits
Addr Match
Addr Match
or General
or General
and