MC68HC705JP7CDW Freescale Semiconductor, MC68HC705JP7CDW Datasheet
MC68HC705JP7CDW
Specifications of MC68HC705JP7CDW
Related parts for MC68HC705JP7CDW
MC68HC705JP7CDW Summary of contents
Page 1
MC68HC705JJ7 MC68HC705JP7 MC68HC705SJ7 MC68HC705SP7 MC68HRC705JJ7 MC68HRC705JP7 Advance Information Data Sheet M68HC05 Microcontrollers MC68HC705JJ7 Rev. 4.1 09/2005 freescale.com This document contains certain information on a new product.Specifications and information herein are subject to change without notice. ...
Page 2
...
Page 3
... Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://www.freescale.com/ Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. © Freescale Semiconductor, Inc., 2005. All rights reserved. MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 ...
Page 4
... Section 15. Electrical Specifications — Added Figure 15-1 through Figure 15-10 and Figure 15-12 September, 4.1 Updated to meet Freescale identity guidelines. 2005 MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 4 Description Freescale Semiconductor Page Number(s) All All 94 96 179 188 189 ...
Page 5
... Chapter 10 Core Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Chapter 11 Programmable Timer 105 Chapter 12 Personality EPROM (PEPROM 115 Chapter 13 EPROM/OTPROM .119 Chapter 14 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Chapter 15 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Chapter 16 Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Chapter 17 Ordering Information 161 MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 Freescale Semiconductor 5 ...
Page 6
... List of Chapters MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 6 Freescale Semiconductor ...
Page 7
... Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.2 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.3 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.4 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.5 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.6 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.7 Arithmetic/Logic Unit (ALU MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 Freescale Semiconductor Chapter 1 General Description Chapter 2 Memory Chapter 3 Central Processor Unit (CPU) 7 ...
Page 8
... COP Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5.5.5 16-Bit Programmable Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5.5.6 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5.5.7 Analog Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5.5.8 External Oscillator and Internal Low-Power Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.2 Oscillator Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 8 Chapter 4 Interrupts Chapter 5 Resets Chapter 6 Operating Modes Freescale Semiconductor ...
Page 9
... Absolute Voltage Readings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 8.6.1.1 Internal Absolute Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 8.6.1.2 External Absolute Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 8.6.2 Ratiometric Voltage Readings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 8.6.2.1 Internal Ratiometric Reference 8.6.2.2 External Ratiometric Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 Freescale Semiconductor Chapter 7 Parallel Input/Output Chapter 8 Analog Subsystem Table of Contents 9 ...
Page 10
... Timer Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 11.8 Timer Operation during Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 11.9 Timer Operation during Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 11.10 Timer Operation during Halt Mode 114 MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 10 Chapter 9 Chapter 10 Core Timer Chapter 11 Programmable Timer Freescale Semiconductor ...
Page 11
... Jump/Branch Instructions 129 14.3.4 Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 14.3.5 Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 14.4 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 14.5 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 Freescale Semiconductor Chapter 12 Personality EPROM (PEPROM) Chapter 13 EPROM/OTPROM Chapter 14 Instruction Set Table of Contents 11 ...
Page 12
... Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 17.2 MC68HC705JJ7 Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 17.3 MC68HC705JP7 Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 12 Chapter 15 Electrical Specifications = 4.5 to 5.5 Vdc 140 DD = 2.7 to 3.3 Vdc 140 DD Chapter 16 Mechanical Specifications Chapter 17 Ordering Information Freescale Semiconductor ...
Page 13
... EPROM array • MOR selectable computer operating properly (COP) watchdog system 1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the EPROM/OTPROM difficult for unauthorized users. MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 Freescale Semiconductor 13 ...
Page 14
... MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 14 NOTE Chapter 15 Electrical for specific ordering information. Pin Oscillator Count Type 20 Crystal/resonator 28 Crystal/resonator 20 Crystal/resonator 28 Crystal/resonator 20 Resistor-capacitor 28 Resistor-capacitor DD Specifications. Table 1-1 and to Internal LPO Nominal Frequency (kHz) 100 100 500 500 100 100 Freescale Semiconductor ...
Page 15
... USER EPROM — 6160 BYTES PERSONALITY EPROM — 64 BITS * High sink current capability * High source current capability † IRQ interrupt capability MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 Freescale Semiconductor 16-BIT TIMER TCAP (1) INPUT CAPTURE TCMP (1) OUTPUT COMPARE ICF ...
Page 16
... PB7/SCK 11 18 *PA5 PA4 13 16 † * PA3 14 15 Figure 1-2. User Mode Pinouts PB0/AN0 OSC1 OSC2 RESET IRQ/V PP † PA0* † PA1* † PA2* PB0/AN0 OSC1 OSC2 PC3* PC2* PC1* PC0* RESET IRQ/V PP † PA0* † PA1* † PA2* Freescale Semiconductor ...
Page 17
... An internal startup resistor of approximately 2 MΩ can be provided between OSC1 and OSC2 for the crystal type oscillator by use of the OSCRES bit in the MOR. MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 Freescale Semiconductor and the positive supply, and V ...
Page 18
... MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 18 (b). NOTE Figure 1-3 (c). This oscillator can be selected via software. This NOTE any charge left on an external capacitor connected DD . The RESET pin also contains an internal Schmitt trigger to improve its Freescale Semiconductor ...
Page 19
... MC68HC705JP7. All eight of these pins have high current source and sink capability. All of these pins have software programmable pulldowns which can be disabled by the SWPDI bit in the MOR. MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 Freescale Semiconductor for “wired-OR” operation. If the IRQ/V DD supply. The IRQ/V ...
Page 20
... General Description MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 20 Freescale Semiconductor ...
Page 21
... The first 32 addresses of the memory space, $0000–$001F, containing the I/O registers section • One I/O register located outside the 32-byte I/O section, which is the computer operating properly register (COPR) mapped at $1FF0 MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 Freescale Semiconductor $1EFF Figure 2-1. Memory Map Figure 2-1. The ...
Page 22
... Input Capture Register (LSB) Output Compare Register (MSB) Output Compare Register (LSB) Timer Counter Register (MSB) Timer Counter Register (LSB) Alternate Counter Register (MSB) Alternate Counter Register (LSB) EPROM Programming Register Analog Control Register Analog Status Register Reserved Figure 2-2. I/O Registers Freescale Semiconductor ...
Page 23
... See page 97. SIOP Status Register $000B (SSR) See page 99. 1. Features related to port C are only available on the 28-pin MC68HC705JP7 devices. Figure 2-3. Register Summary (Sheet MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 Freescale Semiconductor Bit Read PA5 Write: ...
Page 24
... Write: Reset: = Unimplemented IRQF IRQR PEB4 PEB3 PEB2 PEB1 PDIA4 PDIA3 PDIA2 PDIA1 PDIB4 PDIB3 PDIB2 PDIB1 IEDG Unaffected by reset Unaffected by reset Unaffected by reset Unaffected by reset R = Reserved U = Unaffected Freescale Semiconductor Bit 0 Bit PEB0 0 PEPRZF 1 PDIA0 0 PDIB0 0 OLVL Bit 8 Bit 0 Bit 8 Bit 0 ...
Page 25
... COP and Security Register $1FF0 (COPR) See pages 27, 92, 104, and 122. 1. Features related to port C are only available on the 28-pin MC68HC705JP7 devices. Figure 2-3. Register Summary (Sheet MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 Freescale Semiconductor Bit Read: Bit ...
Page 26
... Timer Interrupt Vector (LSB) Core Timer Interrupt Vector (MSB) Core Timer Interrupt Vector (LSB) External IRQ Vector (MSB) External IRQ Vector (LSB) SWI Vector (MSB) SWI Vector (LSB) Reset Vector (MSB) Reset Vector (LSB) Figure 2-4. Vector Mapping NOTE Figure 2-4. Freescale Semiconductor ...
Page 27
... Reset: = Unimplemented Figure 2-5. COP and Security Register (COPR security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the EPROM/OTPROM difficult for unauthorized users. MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 Freescale Semiconductor OPT Unaffected by reset ...
Page 28
... Memory MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 28 Freescale Semiconductor ...
Page 29
... CPU registers are not part of the memory map PCH Figure 3-1. M68HC05 Programming Model 3.2 Accumulator The accumulator is a general-purpose 8-bit register as shown in accumulator to hold operands and results of arithmetic and non-arithmetic operations. Bit 7 Read: Write: Reset: MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 Freescale Semiconductor PCL ...
Page 30
... MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4 Unaffected by reset Figure 3-3. Index Register ( Figure 3-4. Stack Pointer (SP Loaded with vector from $1FFE and $1FFF Figure 3-5. Program Counter (PC) Figure 3-3. In the indexed addressing 2 1 Bit 0 Bit Bit Freescale Semiconductor ...
Page 31
... Multiplication is not performed as a discrete operation but as a chain of addition and shift operations within the ALU. The multiply instruction (MUL) requires 11 internal clock cycles to complete this chain of operations. MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 Freescale Semiconductor ...
Page 32
... Central Processor Unit (CPU) MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 32 Freescale Semiconductor ...
Page 33
... Serial interrupt SPIF bit CPF1 bit Analog interrupt CPF2 bit 1. COPEN enables the COP watchdog timer. 2. PIRQ enables port A external interrupts on PA0–PA3. MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 Freescale Semiconductor NOTE MOR Global Local Control Hardware Software ...
Page 34
... MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 34 Bottom of RAM Bottom of Stack Condition Code Register Accumulator Index Register Program Counter (High Byte) Program Counter (Low Byte) Top of Stack (RAM) Figure 4-1. Interrupt Stacking Order Figure 4-1 Unstacking Order ? › Stacking Order Freescale Semiconductor ...
Page 35
... YES INTERRUPT? CORE TIMER INTERRUPT? INTERRUPT? INTERRUPT? INTERRUPT? FETCH NEXT INSTRUCTION INSTRUCTION? INSTRUCTION? MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 Freescale Semiconductor FROM RESET I BIT SET? NO YES EXTERNAL CLEAR IRQ LATCH NO YES NO TIMER YES NO SERIAL YES NO ANALOG YES NO STACK PCL, PCH CCR ...
Page 36
... MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 36 pin latches an external interrupt request. To help clean up slow edges, PP NOTE NOTE pin can be affected if the external interrupt PP pin. DD pin PP pin latches an external interrupt PP pin PP Freescale Semiconductor ...
Page 37
... The edge- and level-sensitive trigger MOR option allows connection to a PA0:3 pin of multiple wired-OR interrupt sources. As long as any source is holding the pin high, an external interrupt request is present, and the CPU continues to execute the interrupt service routine. MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 Freescale Semiconductor V DD IRQ ...
Page 38
... Table 4-2. Oscillator Selection Internal Oscillator External Pin Low-Power Selected Oscillator Oscillator by CPU (LPO) Internal Enabled Disabled External Disabled Enabled Internal Enabled Disabled Internal Enabled Enabled pin PP pin low level, the 2 1 Bit IRQR Unaffected Power Consumption (EPO) Lowest Normal Lowest Normal Freescale Semiconductor ...
Page 39
... A real-time interrupt request occurs if the real-time interrupt flag (RTIF) in the CTSCR becomes set while the real-time interrupt enable bit (RTIE) is also set. The RTIF flag bit can be reset by writing a logical 1 to the RTIFR bit in the CTSCR reset of the device. MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 Freescale Semiconductor pin PP Core Timer Interrupts ...
Page 40
... SSR with the SPIF flag bit set, and then followed by a read or write to the serial data register (SDR) located at $000C. The SPIF flag bit can also be reset by writing a one to the SPIR bit in the SCR. MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 40 Freescale Semiconductor ...
Page 41
... For the analog subsystem to generate an interrupt using the input capture function of the programmable timer, the ICEN enable bit in the ACR, and the ICIE and IEDG bits in the TCR must all be set. MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 Freescale Semiconductor NOTE Analog Interrupts 4.7.1 Input ...
Page 42
... Interrupts MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 42 Freescale Semiconductor ...
Page 43
... MASK OPTION REGISTER ($1FF1) COP WATCHDOG LOW-VOLTAGE RESET V POWER-ON RESET DD ILLEGAL ADDRESS RESET RESET 3-CYCLE CLOCKED 1-SHOT MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 Freescale Semiconductor INTERNAL DATA BUS INTERNAL ADDRESS BUS Figure 5-1. Reset Sources S TO CPU RST D AND RESET SUBSYSTEMS ...
Page 44
... The power-on reset is strictly for ) after the oscillator becomes active allows the clock cyc NOTE , as this may overload some time, the MCU remains cyc generates an external reset. cyc must drop below V for the internal DD POR Freescale Semiconductor ...
Page 45
... LVR trip voltage. The LVR will assert the pulldown device to pull the RESET pin low for three to four cycles of the internal bus security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the EPROM/OTPROM difficult for unauthorized users. MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 Freescale Semiconductor Figure 5- write-only bit ...
Page 46
... Sets the real-time interrupt (RTI) rate selection bits (RT0 and RT1) such that the device will start with the longest real-time interrupt and longest COP timeout delays 1. Features related to port C are only available on the 28-pin MC68HC705JP7 devices MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 46 NOTE supply voltage DD (1) (1) (1) data registers Freescale Semiconductor ...
Page 47
... OM2 = 1) which has these effects on the oscillators: • The internal low-power oscillator is enabled and selected. • The external oscillator is disabled. • The CPU bus clock is driven from the internal low-power oscillator. MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 Freescale Semiconductor Reset States 47 ...
Page 48
... Resets MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 48 Freescale Semiconductor ...
Page 49
... Therefore, the lowest power is consumed when OM1 is cleared. The state with both OM1 and OM2 set is provided so that the EPO can be started up and allowed to stabilize while the LPO still clocks the MCU. MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 Freescale Semiconductor ...
Page 50
... MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4 Table 6-1. Oscillator Selection Internal External Pin Oscillator Low-Power Oscillator Selected Oscillator (LPO) Internal Enabled Disabled External Disabled Enabled Internal Enabled Disabled Internal Enabled Enabled NOTE for more details. Power Consumption (EPO) Lowest Normal Lowest Normal Freescale Semiconductor ...
Page 51
... OR 2. SERVICE INTERRUPT. a. SAVE CPU REGISTERS ON STACK. b. SET I BIT IN CCR. c. LOAD PC WITH INTERRUPT VECTOR. MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 Freescale Semiconductor HALT YES CLEAR I BIT IN CCR. SET IRQE BIT IN ISCR. TURN OFF CPU CLOCK. KEEP OTHER MODULE CLOCKS ACTIVE ...
Page 52
... If the COP watchdog timer used, stop mode should be changed to halt mode as described in MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 52 pin by setting the IRQE bit in the IRQ status and control PP pin — A high-to-low transition on the IRQ/V PP NOTE 6.3.3 Halt Mode. pin loads PP Freescale Semiconductor ...
Page 53
... MOR. If the SWAIT bit is set in the MOR to put the MCU in halt mode, the COP watchdog cannot be turned off inadvertently by a STOP instruction. MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 Freescale Semiconductor pin — A high-to-low transition on the IRQ/V PP Low-Power Modes ...
Page 54
... The RESET pin must remain low continuously during data retention mode take the MCU out of the data retention mode: 1. Return V to normal operating voltage Return the RESET pin to a logic 1. MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 54 Freescale Semiconductor ...
Page 55
... PA5–PA0 — Port A Data Bits These read/write bits are software programmable. Data direction of each bit is under the control of the corresponding bit in the port A data direction register (DDRA). Reset has no effect on port A data. MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 Freescale Semiconductor ...
Page 56
... Upper four port C pins pulldown devices turned on if pin has been programmed by the DDRC input MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4 DDRA5 DDRA4 DDRA3 Unimplemented PDICL PDIA5 PDIA4 PDIA3 Unimplemented Figure 7-3. Pulldown Register A (PDRA Bit 0 DDRA2 DDRA1 DDRA0 Bit 0 PDIA2 PDIA1 PDIA0 Freescale Semiconductor ...
Page 57
... PA4 (2) PA5 X 1. DDRA can always be read or written. 2. Don’t care MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 Freescale Semiconductor NOTE pin, not the state of the internal IRQ signal. PP Table 7-1. Port A Pin Functions PORTA Access Port A (Pin or Data Register) ...
Page 58
... Unaffected by reset SDI SDO AN4 AN3 SDI SDO TCMP TCAP SDI SDO CMP1 TCAP EXTERNAL INTERRUPT REQUEST (PA0:3) PAx HIGH SINK/SOURCE CURRENT CAPABILITY PULLDOWN DEVICE 2 1 Bit 0 PB2 PB1 PB0 AN2 AN1 AN0 AN2 AN1 AN0 AN2 AN1 AN0 Freescale Semiconductor ...
Page 59
... B bits returns undefined data. Reset clears bits PDIB7–PDIB0 Corresponding port B pin pulldown device turned off 0 = Corresponding port B pin pulldown device turned on if pin has been programmed by the DDRB input MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 Freescale Semiconductor ...
Page 60
... BIT DDRBx R PORT BDATA REGISTER BIT PBx PULLDOWN REGISTER B BIT PDIBx R MASK OPTION REG. ($1FF1) Figure 7-8. PB0–PB3 Pin I/O Circuit Table 7-2. ANALOG SUBSYSTEM, AND PROGRAMMABLE TIMER INPUT CAPTURE (PINS PB0, PB1, PB2, PB3) PBx PULLDOWN DEVICE Freescale Semiconductor ...
Page 61
... OLVL bit. The pulldown device will be disabled in this case. The analog subsystem would not normally use this pin as an analog input in this case. MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 Freescale Semiconductor 7-9. The PB4 data, the programmable timer OLVL bit, and the output of DATA DIRECTION ...
Page 62
... Pin Data On 0 Pin Data Off 0 Pin Data Off 1 Data Data Off 1 Data Data Off 1 Data Data Off 1 1 Data Off 1 1 Data Off Freescale Semiconductor Pin PBx in PBx in PBx in PBx out PB4 in PB4 in PB4 in PB4 out PB4 out PB4 out 1 1 ...
Page 63
... If the PB5/SDO pin digital output, then the SPE bit in the SCR must be cleared and the PDIB5 bit must be set. The pulldown device will be disabled in this case. MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 Freescale Semiconductor V DD DATA DIRECTION ...
Page 64
... MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 64 DATA DIRECTION REGISTER B BIT DDRB6 R PORT B DATA REGISTER BIT PB6 PULLDOWN REGISTER B BIT PDIB6 R MASK OPTION REG. ($1FF1) Figure 7-11. PB6/SDI Pin I/O Circuit Table 7-3. PB6 SDI PULLDOWN DEVICE Freescale Semiconductor ...
Page 65
... If the PB7/SCK pin digital input, then both the SPE bit in the SCR and the DDRB7 bit must be cleared. Depending on the external application, the pulldown device may also be disabled by setting the PDIB7 pulldown inhibit bit. MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 Freescale Semiconductor DATA DIRECTION REGISTER B BIT DDRB7 ...
Page 66
... Data Off PB6 in Data Off PB6 out Data Off SDI in Data Off SDI in Data On PB7 in Data Off PB7 in Data Off PB7 in Data Off PB7 out Data Off SCK in Data Off SCK in Data Off SCK out Data Off SCK out Freescale Semiconductor ...
Page 67
... DDRC7–DDRC0 — Port C Data Direction Bits These read/write bits control port C data direction. Reset clears the DDRC7–DDRC0 bits Corresponding port C pin configured as output and pulldown device disabled 0 = Corresponding port C pin configured as input MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 Freescale Semiconductor ...
Page 68
... MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 68 7-3. PDICH controls the upper four pins (PC7–PC4) and PDICL DATA DIRECTION REGISTER C BIT DDRCx PULLDOWN REGISTER A BIT PDICx MASK OPTION REGISTER ($1FF1) Figure 7-15. Port C I/O Circuit PCx HIGH SINK/SOURCE CURRENT CAPABILITY PULLDOWN DEVICE Freescale Semiconductor ...
Page 69
... Characteristics (5.0 Vdc) ensure that all ganged pins always maintain the same output logic value. MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 Freescale Semiconductor PORTC Access (Pin or Data Register) Port C ...
Page 70
... Parallel Input/Output MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 70 Freescale Semiconductor ...
Page 71
... Input capture in the 16-bit programmable timer • Interrupt generated by the comparator output • Software polling of the comparator output using software loop time MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 Freescale Semiconductor or an external voltage as a reference with software used to DD for calibration SS Figure 8-1 ...
Page 72
... CHG ATD1 ATD2 ISEN CP2EN ICEN CP1EN CPIE $001D ANALOG INTERRUPT CPF2 CPF1 CMP2 CMP1 VOFF $001E OPT (COPR) HOLD DHOLD INV V REF MUX4 MUX3 MUX2 MUX1 COE1 $0003 OPT (COPR) MUX4 DENOTES MUX3 INTERNAL MUX2 ANALOG V SS MUX1 Freescale Semiconductor ...
Page 73
... HOLD or DHOLD bit set. The VOFF bit must be enabled by the OPT bit in the COPR at location $1FF0 INTERNAL TEMPERATURE DIODE CHANNEL SELECTION BUS MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 Freescale Semiconductor 8- DHOLD INV VREF MUX4 0 ...
Page 74
... Signal on channel selection bus is connected (1) (1) No directly to sample capacitor and comparator negative input. Internal temperature sensing diode connected (1) (1) No directly to sample capacitor and comparator negative input. and the internal sample capacitor will be discharged to SS NOTE NOTE Source To Negative Input of Comparator 2 SS Freescale Semiconductor ...
Page 75
... AV circumstances, the positive input (+) to comparator 2 will always be higher than the negative input (–) until the negative input reaches the AV voltage plus any offset in comparator 2. MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 Freescale Semiconductor RISE WHEN V+ V+ > V– ...
Page 76
... All the bits in this register are cleared by a reset of PB2/AN2 PB1/AN1 Hi-Z Hi Hi-Z Hi Hi-Z Hi Hi-Z Hi 15.5 Supply Current Characteristics Freescale Semiconductor Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi ...
Page 77
... Option Control Mode Current source and Disabled discharge disabled Automatic charge and discharge 3 (OCF–ICF) synchronized to timer MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 Freescale Semiconductor ATD2 ATD1 ICEN CPIE Table Table 8-3. A/D Conversion Options A/D Options ISEN ...
Page 78
... The CP1EN enable bit will power down the voltage comparator 1 in the analog subsystem. Powering down a comparator will drop the supply current. This bit is cleared by a reset of the device Writing a logic 1 powers up voltage comparator Writing a logic 0 powers down voltage comparator 1 MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 78 NOTE NOTE NOTE Freescale Semiconductor ...
Page 79
... A positive transition on the output of comparator 1 has occurred since the last time the CPF1 flag has been cleared positive transition on the output of comparator 1 has not occurred since the last time the CPF1 flag has been cleared. MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 Freescale Semiconductor NOTE ...
Page 80
... The voltage on the positive input on comparator 2 is higher than the voltage on the negative input of comparator The voltage on the positive input on comparator 2 is lower than the voltage on the negative input of comparator 2. MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 80 NOTE 8.10 Sample and SS . The VOFF SS Hold. Freescale Semiconductor ...
Page 81
... These three bits will have no effect on the PB0/AN0 pin if the ISEN enable bit is cleared. Any clearing of the ISEN bit will immediately disable both the charge current source and the discharge device. Since all MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 Freescale Semiconductor Charge Time = ...
Page 82
... MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4 CHG EXT X CHG CHG OSC NOTE , can be combined to form the following expression CHG EXT FS OSC EXT FS CHG FS NOTE ). Therefore, the OSC ): FS ) CHG , conversion method, and OSC OSC Freescale Semiconductor ...
Page 83
... Time to discharge external capacitor, C DIS C Capacitance of external ramping capacitor EXT Number of counts for I N CHG MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 Freescale Semiconductor , conversion method, and resolution is defined OSC CHG EXT NOTE through ...
Page 84
... Note 1 1.0 8.192 2.0 4.096 4.0 2.048 0.1 Note 1 1.0 32.768 2.0 16.384 4.0 8.192 Freescale Semiconductor Units ÷ (µF) EXT 0.110 0.011 0.006 0.003 0.037 0.004 0.002 0.001 0.439 0.044 0.022 0.011 0.585 0.059 0.029 ...
Page 85
... CAP MAX Begin next discharge by clearing the CHG 5 control bit in the ACR. Reset CPF2 by writing CPFR2. Figure 8-8. A/D Conversion — Full Manual Control (Mode 0) MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 Freescale Semiconductor t MAX t CHG Software/Hardware Action Software write ...
Page 86
... MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4 DIS (MIN) t CHG Software/Hardware Action Software write Wait out minimum t time. DIS Software write Wait out t time. CHG CPF2 clears CHG control bit. V MAX CHG CHG EXT 2 Dependent Variable(s) Software MAX DIS EXT Software CHG EXT Freescale Semiconductor ...
Page 87
... ICF from the timer and clears the CHG control bit in ACR. Must clear CPF2 to trap next CPF2 flag. Figure 8-10. A/D Conversion — TOF/ICF Control (Mode 2) MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 Freescale Semiconductor t DIS (MIN) t CHG ...
Page 88
... Timer OCF sets the CHG control bit in the ACR. Wait out t time. CHG Timer ICF clears the CHG control bit in the ACR. V MAX CHG CHG EXT 2 Dependent Variable(s) Software software MAX DIS EXT Free-running timer output compare, f OSC CHG EXT Freescale Semiconductor ...
Page 89
... All A/D conversion methods should include a test for a maximum elapsed time to detect error cases where the inputs may be outside of the design specification. MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 Freescale Semiconductor = EXTMIN ...
Page 90
... OR avoid use of divided input Sum two readings on reference or unknown using INV and INV control bit and divide by 2 (average of both) and V pins and Average multiple readings on both the reference DD SS and the unknown voltage 8-6. As can be seen from this range, MAX In Software Freescale Semiconductor ...
Page 91
... MUX bit in the AMUX which connects channel selection bus to the pin connected to the external reference source. If the external reference is greater than V bit should be used to select the 1/2 divided input. MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 Freescale Semiconductor Accuracy Improvements Possible In Hardware Compare unknown with recent measurement ...
Page 92
... Port B Pin Device as Inputs Disable Not DDRB2 = 0 affected DDRB3 = 0 DDRB0 = 0 ISEN = 0 DDRB1 = OPT Unimplemented U = Unaffected Port B Pin Prog. Timer Input Pulldowns Capture Disabled Source PDIB2 = 1 Not PDIB3 = 1 affected PDIB0 = 1 ICEN = 0 PDIB1 = 1 IEDG = 1 Figure 8-12, and the 2 1 Bit 0 COPC Freescale Semiconductor ...
Page 93
... HOLD and DHOLD bits when the VOFF is active. Refer to Register for more details on the design and decoding of the sample and hold circuit. MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 Freescale Semiconductor and will have its voltage change Register). ...
Page 94
... A noise reduction benefit can be gained with 0.1-µF bypass capacitors from each analog input (PB4:1) to the V pin. Also, try to keep all the digital power supply or load currents from passing through any SS conductors which are the return paths for an analog signal. MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 94 return for both SS Freescale Semiconductor ...
Page 95
... CPHA MSTR SPE LSBF SPIR SPIE $000A LATCH SIOP Q INTERRUPT SPIF DCOL $000B MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 Freescale Semiconductor CLOCK CONTROL DIN CLK 8-BIT SHIFT COMP S REGISTER ERROR R FORMAT CONTROL (LSB OR MSB FIRST) SIOP DATA REGISTER ...
Page 96
... When the CPHA is set, SCK will remain idle at BIT 2 BIT 3 BIT 4 BIT 5 100 ns BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 2 BIT 3 BIT 4 BIT 5 100 ns BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 (IDLE = 1) 100 ns BIT 7 BIT 8 BIT 6 BIT 7 BIT 8 100 ns BIT 6 BIT 7 BIT 8 Freescale Semiconductor ...
Page 97
... Serial interrupt disabled If the SPIE bit is cleared just after the serial interrupt sequence has started (for instance, the CPU status is being stacked), then the CPU will be unable MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 Freescale Semiconductor Figure 9-3. Figure 9-4 ...
Page 98
... PB7/SCK pin when the device is configured with the SIOP as a master (MSTR = 1). The fastest rate is when both SPR0 and SPR1 are set. Both the SPR0 and SPR1 bits are cleared by reset, which places the SIOP clock selection at the slowest rate. MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 98 Table 9 supplied on the Freescale Semiconductor ...
Page 99
... DCOL bit will be set again. Reset clears the DCOL bit Illegal access of the SDR occurred illegal access of the SDR detected MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 Freescale Semiconductor Table 9-1. SIOP Clock Rate Selection SIOP Clock Rate SPR0 ...
Page 100
... This register is not affected by reset. Address: $000C Bit 7 Read: Bit 7 Write: Reset: MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 100 Unaffected by reset Figure 9-6. SIOP Data Register (SDR Bit Bit 0 Freescale Semiconductor ...
Page 101
... This section describes the operation of the core timer and the computer operating properly (COP) watchdog as shown by the block diagram in OVERFLOW CORE TIMER COUNTER REGISTER $1FF0 COPR REGISTER RESET MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 Freescale Semiconductor Figure 10-1. $0009 ÷ 4 BITS 0–7 OF 15-STAGE RIPPLE COUNTER CORE TIMER STATUS/CONTROL REGISTER RTI RATE SELECT ÷ ...
Page 102
... RTI output drives the COP watchdog, changing the real -time interrupt rate also changes the MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 102 RTIF 0 CTOFE RTIE CTOFR Unimplemented Figure 2 1 Bit 0 0 RT1 RT0 RTIFR Table 10-1. Because the Freescale Semiconductor 10-2. ...
Page 103
... COPEN bit in the MOR. The COP watchdog is a software error detection system that automatically times out and resets the MCU if the COP watchdog is not cleared MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 Freescale Semiconductor NOTE Real-Time ...
Page 104
... V PP pin voltage falls below PP SWAIT Wait/Halt Time (1) (in MOR) Less than COP 1 timeout period Greater than COP 1 timeout period ( ( Bit 0 COPC Table 10-2 summarizes recommended , the COP watchdog DD Recommended COP Watchdog Condition (2) Enabled Disabled Disabled Disabled Freescale Semiconductor ...
Page 105
... The interrupt capability, the input capture edge, and the output compare state are controlled by the timer control register (TCR) located at $0012, and the status of the interrupt flags can be read from the timer status register (TSR) located at $0013. MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 Freescale Semiconductor Figure 11-1. 105 ...
Page 106
... ICRL ($0015) LOGIC TMRH ($0018) TMRL ($0019) 16-BIT COUNTER 16-BIT COMPARATOR OCRH ($0016) OCRL ($0017) TIMER STATUS REGISTER ACRH ($001A) ACRL ($001B) INTERNAL ÷ 4 CLOCK (OSC ÷ 2) PB4 D Q PIN I/O AN4 LOGIC TCMP C ANALOG COMP 1 TIMER INTERRUPT REQUEST $0013 Freescale Semiconductor ...
Page 107
... Bit 7 Read: Bit 7 Write: Reset: 1 Figure 11-3. Programmable Timer Registers (TMRH and TMRL) MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 Freescale Semiconductor LATCH TMRL ($0019) TMRH ($0018) TMR LSB 16-BIT COUNTER OVERFLOW (TOF) TIMER CONTROL REG. TIMER STATUS REG. ...
Page 108
... MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 108 NOTE LATCH ACRL ($001B) ACRH ($001A) TMR LSB 16-BIT COUNTER Figure 11 Unimplemented INTERNAL DATA BUS READ ACRL INTERNAL ÷ 4 CLOCK (OSC ÷ 2) are read-only locations which 2 1 Bit Bit Bit Bit Freescale Semiconductor ...
Page 109
... Latching values into the input capture registers at successive edges of the same polarity measures the period of the selected input signal. Latching the counter values at successive edges of opposite polarity measures the pulse width of the signal. MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 Freescale Semiconductor NOTE NOTE EDGE ...
Page 110
... MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 110 Unaffected by reset Unaffected by reset = Unimplemented NOTE Figure 11-8. Software writes the selected value into the output 11-9. These registers are read/write bits and are unaffected by reset Bit Bit Bit Bit 0 Freescale Semiconductor ...
Page 111
... Enable the output compare registers by writing to the OCRL. This also clears the OCF flag bit in the TSR. 5. Enable interrupts by clearing the I bit in the condition code register. A software example of this procedure is shown in MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 Freescale Semiconductor OCRH ($0016) OCRL ($0017) 16-BIT COMPARATOR 16-BIT COUNTER ...
Page 112
... MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 112 DISABLE INTERRUPTS ..... ..... OCRH INHIBIT OUTPUT COMPARE TSR ARM OCF FLAG FOR CLEARING OCRL READY FOR NEXT COMPARE, OCF CLEARED ..... ..... ENABLE INTERRUPTS Figure 11-10, performs the following functions OCIE TOIE Unimplemented U = Unaffected 2 1 Bit 0 0 IEDG OLVL Freescale Semiconductor ...
Page 113
... Clear the OCF bit by reading the timer status register with the OCF set and then accessing the low byte (OCRL, $0017) of the output compare registers. Resets have no effect on OCF. MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 Freescale Semiconductor NOTE Figure 11-11 contains flags for these events: ...
Page 114
... Timer Operation during Halt Mode When the MCU enters halt mode, the functions and states of the 16-bit programmable timer are the same as for wait mode described in 11.8 Timer Operation during Wait MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 114 Mode. Freescale Semiconductor ...
Page 115
... SINGLE SENSE AMPLIFIER 8-TO-1 COLUMN DECODER V SWITCH PP PEPROM BIT SELECT REGISTER INTERNAL DATA BUS Figure 12-1. Personality EPROM Block Diagram MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 Freescale Semiconductor NOTE $000F RESET V PP ROW 0 ROW 1 ROW 2 ROW 3 ROW 4 ROW 5 ...
Page 116
... PEPROM data is a logic PEPROM data is a logic 0. MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 116 PEB6 PEB5 PEB4 PEB3 PEPGM Unimplemented R = Reserved 2 1 Bit 0 PEB2 PEB1 PEB0 Table 12-1. Bits PEB2–0 select 2 1 Bit PEPRZF Unaffected Freescale Semiconductor ...
Page 117
... Set the PEPGM bit in the PESCR. 3. Wait for the programming time Clear the PEPGM bit. 5. Move to next PEPROM bit to be programmed in step 1. MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 Freescale Semiconductor Table 12-1. PEPROM Bit Selection PEBSR PEPROM Bit Selected $00 ...
Page 118
... Ws/cm of ultraviolet light with a wavelength of 2537 angstroms. Position the ultraviolet light source 1 inch from the window. Do not use a shortwave filter. The erased state of a PEPROM bit is a logic 0. MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 118 NOTE Freescale Semiconductor ...
Page 119
... EPROM programming power switched off MPGM — Mask Option Register (MOR) Programming Bit This read/write bit applies programming power from the IRQ MOR programming power switched MOR programming power switched off MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 Freescale Semiconductor NOTE Figure 13 ...
Page 120
... This EPROM bit inhibits software control of the port A and port B pulldown devices Software pulldown inhibited 0 = Software pulldown enabled MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 120 Figure 13 EPROM byte that controls eight mask options DELAY OSCRES SWAIT LVREN Unaffected by reset EPGM 2 1 Bit 0 PIRQ LEVEL COPEN Freescale Semiconductor ...
Page 121
... PA3–PA0 pins positive-edge triggered only PP COPEN — COP Watchdog Enable Bit This EPROM bit enables the COP watchdog COP watchdog enabled 0 = COP watchdog disabled MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 Freescale Semiconductor CAUTION NOTE EPROM Registers 121 ...
Page 122
... No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the EPROM/OTPROM difficult for unauthorized users. MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 122 OPT Unaffected by reset — — — — = Unimplemented (1) NOTE 13.3.2 EPMSEC 2 1 Bit 0 COPC — — — Freescale Semiconductor ...
Page 123
... Do not use a shortwave filter. The erased state of an EPROM bit is a logic 0. Unlike many commercial EPROMs, an erased EPROM byte in the MCU will read as $00. All unused locations should be programmed as 0s. MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 Freescale Semiconductor pin MPGM pin ...
Page 124
... EPROM/OTPROM MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 124 Freescale Semiconductor ...
Page 125
... Direct instructions can access any of the first 256 memory locations with two bytes. The first byte is the opcode, and the second is the low byte of the operand address. In direct addressing, the CPU automatically uses $00 as the high byte of the operand address. MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 Freescale Semiconductor 125 ...
Page 126
... When using the Freescale assembler, the programmer does not need to calculate the offset, because the assembler determines the proper offset and verifies that it is within the span of the branch. MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 126 Freescale Semiconductor ...
Page 127
... OR Accumulator with Memory Byte Subtract Memory Byte and Carry Bit from Accumulator Store Accumulator in Memory Store Index Register in Memory Subtract Memory Byte from Accumulator MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 Freescale Semiconductor Instruction Instruction Types Mnemonic ADC ADD ...
Page 128
... TST is an exception to the read-modify-write sequence because it does not write a replacement value. MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 128 NOTE Instruction Mnemonic ASL ASR BCLR BSET CLR COM DEC INC LSL LSR NEG ROL ROR TST (1) (1) (2) Freescale Semiconductor ...
Page 129
... Branch if Not Equal Branch if Plus Branch Always Branch if Bit Clear Branch Never Branch if Bit Set Branch to Subroutine Unconditional Jump Jump to Subroutine MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 Freescale Semiconductor Instruction Mnemonic BCC BCS BEQ BHCC BHCS BHI BHS ...
Page 130
... Stop CPU Clock and Enable Interrupts MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 130 Instruction Table 14-5. Control Instructions Instruction Pin PP Mnemonic BCLR BRCLR BRSET BSET Mnemonic CLC CLI NOP RSP RTI RTS SEC SEI STOP SWI TAX TXA WAIT Freescale Semiconductor ...
Page 131
... Branch if Equal Branch if Half-Carry BHCC rel Bit Clear Branch if Half-Carry BHCS rel Bit Set BHI rel Branch if Higher MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 Freescale Semiconductor . Description H A ← (A) + (M) + (C) A ← (A) + (M) A ← (A) ∧ (M) — — — — C ...
Page 132
... EXT — IX2 IX1 REL REL REL REL REL REL REL REL DIR (b0 DIR (b1 DIR (b2 DIR (b3 DIR (b4 DIR (b5 DIR (b6 DIR (b7 DIR (b0 DIR (b1 DIR (b2 DIR (b3 DIR (b4 DIR (b5 DIR (b6 DIR (b7 REL DIR (b0 DIR (b1) 12 DIR (b2 DIR (b3 DIR (b4 DIR (b5 DIR (b6 DIR (b7 Freescale Semiconductor ...
Page 133
... INC ,X JMP opr JMP opr JMP opr,X Unconditional Jump JMP opr,X JMP ,X MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 Freescale Semiconductor Description H PC ← (PC push (PCL) SP ← (SP) – 1; push (PCH) — — — — — SP ← (SP) – ← (PC) + rel C ← ...
Page 134
... EXT — IX2 IX1 DIR INH 48 3 ⋅ INH 58 3 IX1 DIR INH 44 3 INH 54 3 IX1 INH 42 11 DIR INH 40 3 INH 50 3 IX1 INH 9D 2 IMM DIR EXT — IX2 IX1 DIR INH 49 3 INH 59 3 IX1 Freescale Semiconductor ...
Page 135
... Subtract Memory Byte SUB opr from SUB opr,X Accumulator SUB opr,X SUB ,X SWI Software Interrupt MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 Freescale Semiconductor Description H C — — ← $00FF — — — — — SP ← (SP Pull (CCR) SP ← (SP Pull (A) SP ← ...
Page 136
... Zero flag # Immediate value ∧ Logical AND ∨ Logical OR ⊕ Logical EXCLUSIVE Contents of –( ) Negation (two’s complement) ← Loaded with ? If : Concatenated with Set or cleared — Not affected INH 97 2 DIR INH 4D 3 INH 5D 3 IX1 INH 9F 2 INH 8F 2 Freescale Semiconductor ...
Page 137
Bit Manipulation Branch Read-Modify-Write DIR DIR REL DIR INH MSB LSB BRSET0 BSET0 BRA NEG NEGA 3 DIR 2 DIR 2 REL 2 DIR BRCLR0 ...
Page 138
... Instruction Set MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 138 Freescale Semiconductor ...
Page 139
... Operating Temperature Range Characteristic Operating temperature range Extended 15.4 Thermal Characteristics Characteristic Thermal resistance Plastic DIP SOIC MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 Freescale Semiconductor pin only) and V SS NOTE for guaranteed operating conditions. and V within the range In Out ...
Page 140
... OSC2 (2) Min Max Unit Typ µA — 70 320 µA — 320 800 — 1.25 2.60 mA µA — µA — 40 250 — 0.50 1.10 mA µA — — µA — — 380 475 = OSC2 Freescale Semiconductor ...
Page 141
... Figure 15-3. Typical Run I MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 Freescale Semiconductor Supply Current Characteristics (V 0.5 1 1.5 FREQUENCY IN MHz versus Internal Clock Frequency at 25° ...
Page 142
... MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 142 3 3.5 4 4.5 5 SUPPLY VOLTAGE IN VOLTS with External Oscillator DD 3 3.5 4 4.5 5 SUPPLY VOLTAGE IN VOLTS with Analog and LVR Disabled DD –40°C 25°C 85°C 5.5 6 –40°C 25°C 85°C 5.5 6 Freescale Semiconductor ...
Page 143
... PA0–PA5, PB0–PB7, PC0–PC7 1. +4.5 ≤ V ≤ +5 All values shown reflect average measurements. 3. Typical values at midpoint of voltage range, 25°C only. 4. PC0–PC7 parameters only apply to MC68HC705JP7. MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 Freescale Semiconductor (1), (2) Symbol (4) V (4) (4) ...
Page 144
... –0.8 — — –0.8 — — DD — — 0.3 OL — — 0.3 — — — — — — — — — 0 — –1 — — — In –3 — — –2 — Freescale Semiconductor Unit µA µA mA µA µA ...
Page 145
... Temperature diode connection (HOLD = 1, DHOLD = 1) Leakage discharge rate Internal temperature sensing diode Voltage 25°C J Temperature change in voltage 1. +4.5 ≤ V ≤ +5 MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 Freescale Semiconductor NOTE See Figure 15-6. (1) SS –1.5 Vdc) DD ≤ T ≤ unless otherwise noted L ...
Page 146
... I — CHG 1 — I DIS –1.5 CAP DIS C — 2 EXT — SHCHG t 2 — SHDCHG 1 — t SHTCHG — 0.1 C SHDIS V 0.65 0. 1.8 2.0 D Freescale Semiconductor Unit mV V kΩ kΩ kΩ mV kΩ µA % ms/µF µF pF µs µs µs V/sec V mV/°C ...
Page 147
... Figure 15-6. Typical Temperature Diode Performance MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 Freescale Semiconductor Analog Subsystem Characteristics (3.0 Vdc) –15 – TEMPERATURE IN ° 147 ...
Page 148
... TL t 284 — ILIH (3) t — ILIL 110 — CPROP — — 2 CDELAY t — 1 ISTART — IDELAY — BDELAY Freescale Semiconductor Unit MHz MHz MHz kHz kHz MHz MHz MHz kHz kHz ns µs µs t cyc cyc ns µs µs µs µs µs ...
Page 149
... Not offered with the RC oscillator option. 3. The minimum period should not be less than the number of cycle times it takes to execute the interrupt service routine ILIL plus cyc MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 Freescale Semiconductor (1) /2) OSC ) ) ≤ T ≤ T ...
Page 150
... Figure 15-8. Typical 100 kHz External Low-Power MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 150 –25 –15 – TEMPERATURE IN °C Oscillator Frequency –25 –15 – TEMPERATURE IN °C Oscillator Frequency Freescale Semiconductor ...
Page 151
... Figure 15-10. Typical RC Oscillator Internal Operating Frequency Range versus Resistance for Low V MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 Freescale Semiconductor 24.9 EXTERNAL RESISTOR VALUE (kΩ) Operating Range 25°C 24.9 EXTERNAL RESISTOR VALUE (kΩ) Operating Range 25°C Control Timing (3 ...
Page 152
... MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 152 (1) Symbol ) EPGM ) EPGM t MPGM ≤ T ≤ unless otherwise noted NOTE Min Typ Max 16.0 16.5 17.0 — 3.0 5.0 4.0 — — 16.0 16.5 17.0 — 3.0 5.0 4.0 — — 10.0 — — Freescale Semiconductor Unit ...
Page 153
... SDI setup time SDI hold time 1. +4.5 ≤ V ≤ +5 SCK t SCKL SCK t V SDO MSB MSB SDI MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 Freescale Semiconductor = 5.0 Vdc) Symbol Min f 0. SIOP( SIOP( SCK(M) t — SCK(M) t 952 SCKL t — ...
Page 154
... Typ Max 3.4 4.4 3.3 4.3 70 — 0 — 100 — 0.1 — 0.05 — — 3 — Freescale Semiconductor Unit kHz µ Unit V/µs t CYC t CYC ...
Page 155
... COP watchdog timeout 2.Only if reset occurs during normal delay of 4064 t or stop recovery. 3.Internal timing signal and data information not available externally Figure 15-14. Internal Reset Timing Diagram MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 Freescale Semiconductor (2) 4064 cyc 1FFE 1FFF ...
Page 156
... Figure 15-15. Low-Voltage Reset Timing Diagram MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 156 (2) 4064 cyc 1FFE NEW PCH t t for initial power-up or short delay option of 16 cyc cyc V LVRR V LVRF 1FFF NEW PCH NEW PCL NEW PCL Freescale Semiconductor ...
Page 157
... The following figures show the latest package drawings at the time of this publication. To make sure that you have the latest package specifications, contact your local Freescale Sales Office. 16.2 20-Pin Plastic Dual In-Line Package (Case 738) - -T- SEATING PLANE MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 Freescale Semiconductor 0.25 (0.010 ...
Page 158
... BSC 0.100 BSC H 1.65 2.16 0.065 0.085 J 0.20 0.38 0.008 0.015 K 2.92 3.43 0.115 0.135 L 15.24 BSC 0.600 BSC M 0° 15° 0° 15° N 0.51 1.02 0.020 0.040 Freescale Semiconductor MAX 0.510 0.299 0.104 0.019 0.035 0.012 0.009 7° 0.415 0.029 ...
Page 159
... D 28X 0.010 (0.25 -T- G 26X 16.6 20-Pin Windowed Ceramic Integrated Circuit (Case 732 SEATING PLANE MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 Freescale Semiconductor 28-Pin Small Outline Integrated Circuit (Case 751F 14X 0.010 (0.25 - 45° C -T- SEATING PLANE K ...
Page 160
... B 0.500 0.605 12.70 15.36 C 0.160 0.240 4.06 6.09 D 0.015 0.022 0.38 0.55 F 0.050 0.065 1.27 1.65 G 0.100 BSC 2.54 BSC J 0.008 0.012 0.20 0.30 K 0.125 0.160 3.17 4.06 L 0.600 BSC 15.24 BSC 0.020 0.050 0.51 1.27 Freescale Semiconductor ...
Page 161
... Small outline integrated circuit package (DW, case outline 751D) 4. Windowed ceramic dual in-line package (S, case outline 732) 5. CERDIP parts are only guaranteed at room temperature and are for evoluation purposes only. MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1 Freescale Semiconductor LPO Operating Frequency ...
Page 162
... RC 100 –40 to 85°C RC 100 –40 to 85°C RC 100 –40 to 85°C 500 –40 to 85°C 500 –40 to 85°C 500 –40 to 85°C Order Number MC68HC705JP7CP MC68HC705JP7CDW MC68HC705JP7S MC68HRC705JP7CP MC68HRC705JP7CDW MC68HRC705JP7S MC68HC705SP7CP MC68HC705SP7CDW MC68HC705SP7S Freescale Semiconductor ...
Page 163
...
Page 164
... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...