MC68HC705JP7CDW Freescale Semiconductor, MC68HC705JP7CDW Datasheet - Page 81

• Manufacturer Part Number: MC68HC705JP7CDW
• Description: IC MCU 8BIT 28-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of MC68HC705JP7CDW

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 2.1MHz
• Connectivity: SIO
• Peripherals: POR, Temp Sensor, WDT
• Number Of I /o: 22
• Program Memory Size: 6KB (6K x 8)
• Program Memory Type: OTP
• Ram Size: 224 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

CMP1
8.5 A/D Conversion Methods
The control bits in the ACR provide various options to charge or discharge current through the PB0/AN0
pin to perform single-slope A/D conversions using an external capacitor from the PB0/AN0 pin to V
shown in
The top three bits of the ACR control the charging and discharging current into or out of the PB0/AN0 pin.
These three bits will have no effect on the PB0/AN0 pin if the ISEN enable bit is cleared. Any clearing of
the ISEN bit will immediately disable both the charge current source and the discharge device. Since all
Freescale Semiconductor
This read-only bit shows the state of comparator 1 during the time that the bit is read. This bit is
therefore the current state of the comparator without any latched history. The CMP1 bit will be high if
the voltage on the PB2/AN2 pin is greater than the voltage on the PB3/AN3/TCAP pin, regardless of
the state of the INV bit in the AMUX register. Since a reset disables comparator 1, this bit returns a
logic 0 following a reset of the device.
1 = The voltage on the positive input on comparator 1 is higher than the voltage on the negative
0 = The voltage on the positive input on comparator 1 is lower than the voltage on the negative input
Figure
input of comparator 1.
of comparator 1.
VOLTAGE ON
CONNECTED
TO (+) INPUT
CAPACITOR
8-7. The various A/D conversion triggering options are given in
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
OR REFERENCE
Figure 8-7. Single-Slope A/D Conversion Method
UNKNOWN
SIGNALS
TO MATCH UNKNOWN
CHARGE TIME
Charge Time =
MAXIMUM CHARGE TIME
RAMP
CAP
TO V
DD
–1.5 Vdc
PB4/AN4
PB3/AN3
PB2/AN2
PB1/AN1
PB0/AN0
C x V
I
X
MC68HC705JJ7
MC68HC705JP7
+ 5 V
UNKNOWN VOLTAGE ON (–) INPUT
V
V
DD
SS
V
DISCHARGE TIME
TO RESET CAPACITOR
DD
–1.5 Vdc
Table
A/D Conversion Methods
8-3.
SS
as
81