MC68HC705JP7CDW Freescale Semiconductor, MC68HC705JP7CDW Datasheet - Page 61

• Manufacturer Part Number: MC68HC705JP7CDW
• Description: IC MCU 8BIT 28-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of MC68HC705JP7CDW

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 2.1MHz
• Connectivity: SIO
• Peripherals: POR, Temp Sensor, WDT
• Number Of I /o: 22
• Program Memory Size: 6KB (6K x 8)
• Program Memory Type: OTP
• Ram Size: 224 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

7.3.6 PB4/AN4/TCMP/CMP1 Logic
The PB4/AN4/TCMP/CMP1 pin can be used as a simple I/O port pin, be controlled by the OLVL bit from
the output compare function of the 16-bit programmable timer, or be controlled directly by the output of
comparator 1 as shown in
comparator 1 are all logically ORed together to drive the pin. Also, the analog subsystem input channel 4
multiplexer is connected directly to this pin. The operations of PB4 pin are summarized in
When using the PB4/AN4/TCMP/CMP1 pin, these interactions must be noted:
Freescale Semiconductor
1. If the OLVL timer output compare function is the required output function, then the DDRB4 bit must
2. If the PB4 data bit is the required output function, then the DDRB4 bit must be set, the OLVL bit in
3. If the comparator 1 output is the desired output function, then the PB4 data bit must be cleared, the
be set, the PB4 data bit must be cleared, and the OPT bit in the COPR must be cleared. The
PB4/AN4/TCMP/CMP1 pin becomes an output which follows the state of the OLVL bit. The
pulldown device will be disabled in this case. The analog subsystem would not normally use this
pin as an analog input in this case.
the TCR must be cleared, and the OPT bit in the COPR must be cleared. The pulldown device will
be disabled in this case. The analog subsystem would not normally use this pin as an analog input
in this case.
DDRB4 bit must be set, the OLVL bit in the TCR must be cleared, and the OPT bit in the COPR
must be set. The PB4/AN4/TCMP/CMP1 pin becomes an output which follows the state of the
OLVL bit. The pulldown device will be disabled in this case. The analog subsystem would not
normally use this pin as an analog input in this case.
WRITE $0011
WRITE $0001
WRITE $0005
READ $0005
READ $0001
RESET
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
(TIMER OUTPUT COMPARE)
Figure
Figure 7-9. PB4/AN4/TCMP/CMP1 Pin I/O Circuit
(COMPARATOR 1 OUT)
R
R
PORT BDATA
REGISTER
7-9. The PB4 data, the programmable timer OLVL bit, and the output of
DATA DIRECTION
BIT PB4
REGISTER B
REGISTER B
PULLDOWN
BIT DDRB4
BIT PDIB4
CMP1
OLVL
COP REGISTER ($1FF0)
MASK OPTION REG. ($1FF1)
TIMER OUTPUT COMPARE
ANALOG SUBSYSTEM
INPUT AN4 AND
PULLDOWN
DEVICE
SOURCE CURRENT
TCMP
AN4
PB4
CAPABILITY
HIGH SINK/
Table
7-2.
Port B
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