MC68HC705JP7CDW Freescale Semiconductor, MC68HC705JP7CDW Datasheet - Page 56

• Manufacturer Part Number: MC68HC705JP7CDW
• Description: IC MCU 8BIT 28-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of MC68HC705JP7CDW

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 2.1MHz
• Connectivity: SIO
• Peripherals: POR, Temp Sensor, WDT
• Number Of I /o: 22
• Program Memory Size: 6KB (6K x 8)
• Program Memory Type: OTP
• Ram Size: 224 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Parallel Input/Output
7.2.2 Data Direction Register A
The contents of the port A data direction register (DDRA) determine whether each port A pin is an input
or an output. Writing a logic 1 to a DDRA bit enables the output buffer for the associated port A pin. A
DDRA bit set to a logic 1 also disables the pulldown device for that pin. Writing a logic 0 to a DDRA bit
disables the output buffer for the associated port A pin. The upper two bits always read as logic 0s. A reset
initializes all DDRA bits to logic 0s, configuring all port A pins as inputs and disabling the voltage
comparators from driving PA4 or PA5.
DDRA5–DDRA0 — Port A Data Direction Bits
7.2.3 Pulldown Register A
All port A pins can have software programmable pulldown devices enabled or disabled globally by SWPDI
bit in the MOR. These pulldown devices are controlled by the write-only pulldown register A (PDRA)
shown in
A pin is an input. Reading the PDRA returns undefined results since it is a write-only register; therefore,
do not change the value in PDRA with read/modify/write instructions. On the MC68HC705JP7 the PDRA
contains two pulldown control bits (PDICH and PDICL) for port C. Reset clears the PDIA5–PDIA0, PDICH,
and PDICL bits, which turns on all the port A and port C pulldown devices.
PDICH — Upper Port C Pulldown Inhibit Bits (MC68HC705JP7)
56
These read/write bits control port A data direction. Reset clears the DDRA5–DDRA0 bits.
Writing to this write-only bit controls the port C pulldown devices on the upper four bits (PC4–PC7).
Reading these pulldown register A bits returns undefined data. Reset clears bit PDICH.
1 = Corresponding port A pin configured as output and pulldown device disabled
0 = Corresponding port A pin configured as input
1 = Upper four port C pins pulldown devices turned off
0 = Upper four port C pins pulldown devices turned on if pin has been programmed by the DDRC
Figure
to be an input
Address:
Address:
Reset:
Read:
Write:
7-3. Clearing the PDIA5–PDIA0 bits in the PDRA turns on the pulldown devices if the port
Reset:
Read:
Write:
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
$0010
PDICH
$0004
Bit 7
Bit 7
0
0
0
Figure 7-2. Data Direction Register A (DDRA)
Figure 7-3. Pulldown Register A (PDRA)
= Unimplemented
= Unimplemented
PDICL
6
0
6
0
0
PDIA5
DDRA5
5
0
5
0
DDRA4
PDIA4
4
0
4
0
DDRA3
PDIA3
3
0
3
0
DDRA2
PDIA2
2
0
2
0
DDRA1
PDIA1
1
0
1
0
Freescale Semiconductor
DDRA0
Bit 0
PDIA0
0
Bit 0
0