MC68HC705JP7CDW Freescale Semiconductor, MC68HC705JP7CDW Datasheet - Page 55

• Manufacturer Part Number: MC68HC705JP7CDW
• Description: IC MCU 8BIT 28-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of MC68HC705JP7CDW

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 2.1MHz
• Connectivity: SIO
• Peripherals: POR, Temp Sensor, WDT
• Number Of I /o: 22
• Program Memory Size: 6KB (6K x 8)
• Program Memory Type: OTP
• Ram Size: 224 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Chapter 7
Parallel Input/Output
7.1 Introduction
The MC68HC705JJ7 has 14 bidirectional input/output (I/O) pins which form two parallel I/O ports, A
and B. The MC68HC705JP7 has 22 bidirectional I/O pins which form three parallel I/O ports, A, B and C.
Each I/O pin is programmable as an input or an output. The contents of the data direction registers
determine the data direction of each of the I/O pins. All I/O pins have software programmable pulldown
devices which can be enabled or disabled globally by the SWPDI bit in the mask option register (MOR).
7.2 Port A
Port A is a 6-bit, general-purpose, bidirectional I/O port with these features:
7.2.1 Port A Data Register
The port A data register (PORTA) contains a bit for each of the port A pins. When a port A pin is
programmed to be an output, the state of its data register bit determines the state of the output pin. When
a port A pin is programmed to be an input, reading the port A data register returns the logic state of the
pin. The upper two bits of the port A data register will always read as logic 0s.
PA5–PA0 — Port A Data Bits
Freescale Semiconductor
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These read/write bits are software programmable. Data direction of each bit is under the control of the
corresponding bit in the port A data direction register (DDRA). Reset has no effect on port A data.
Individual programmable pulldown devices
High current sinking capability on all port A pins, with a maximum total for port A
High current sourcing capability on all port A pins, with a maximum total for port A
External interrupt capability (pins PA3–PA0)
Alternate:
Address:
Reset:
Read:
Write:
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
$0000
Bit 7
0
Figure 7-1. Port A Data Register (PORTA)
= Unimplemented
6
0
PA5
5
Unaffected by reset
PA4
4
KYBD3
PA3
3
KYBD2
PA2
2
KYBD1
PA1
1
KYBD0
Bit 0
PA0
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