MC68HC705JP7CDW Freescale Semiconductor, MC68HC705JP7CDW Datasheet - Page 104

• Manufacturer Part Number: MC68HC705JP7CDW
• Description: IC MCU 8BIT 28-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of MC68HC705JP7CDW

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 2.1MHz
• Connectivity: SIO
• Peripherals: POR, Temp Sensor, WDT
• Number Of I /o: 22
• Program Memory Size: 6KB (6K x 8)
• Program Memory Type: OTP
• Ram Size: 224 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Core Timer
periodically by a program sequence. Writing a logic 0 to COPC bit in the COPR register clears the COP
watchdog and prevents a COP reset.
EPMSEC — EPROM Security
OPT — Optional Features Bit
COPC — COP Clear Bit
1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the EPROM/OTPROM
104
difficult for unauthorized users.
The EPMSEC bit is a write-only security bit to protect the contents of the user EPROM code stored in
locations $0700–$1FFF.
The OPT bit enables two additional features: direct drive by comparator outputs to port A and voltage
offset capability to sample capacitor in analog subsystem.
This write-only bit resets the COP watchdog. The COP watchdog is active in the run, wait, and halt
modes of operation if the COP is enabled by setting the COPEN bit in the MOR. The STOP instruction
disables the COP watchdog by clearing the counter and turning off its clock source.
In applications that depend on the COP watchdog, the STOP instruction can be disabled by setting the
SWAIT bit in the MOR. In applications that have wait cycles longer than the COP timeout period, the
COP watchdog can be disabled by clearing the COPEN bit.
conditions for enabling and disabling the COP watchdog.
1 = Optional features enabled
0 = Optional features disabled
Address:
Less than 1.5 × V
Less than 1.5 × V
Less than 1.5 × V
More than 1.5 × V
1. The SWAIT bit in the MOR converts STOP instructions to HALT instructions.
2. Reset the COP watchdog immediately before executing the WAIT/HALT instruction.
3. Don’t care
If the voltage on the IRQ/V
turns off and remains off until the IRQ/V
1.5 × V
Reset:
Read:
Write:
IRQ/V
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Voltage on
DD
EPMSEC
$1FF0
PP
Bit 7
.
Pin
Figure 10-4. COP and Security Register (COPR)
Table 10-2. COP Watchdog Recommendations
DD
DD
DD
DD
((1)) Bit
= Unimplemented
OPT
6
(in MOR)
SWAIT
X
1
1
0
PP
5
(1)
pin exceeds 1.5 × V
NOTE
Unaffected by reset
Greater than COP
Wait/Halt Time
Less than COP
timeout period
timeout period
4
PP
X
X
(3)
(3)
pin voltage falls below
3
Table 10-2
DD
, the COP watchdog
2
Watchdog Condition
Recommended COP
summarizes recommended
Enabled
Disabled
Disabled
Disabled
1
(2)
Freescale Semiconductor
COPC
Bit 0