MC68HC705JP7CDW Freescale Semiconductor, MC68HC705JP7CDW Datasheet - Page 59

• Manufacturer Part Number: MC68HC705JP7CDW
• Description: IC MCU 8BIT 28-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of MC68HC705JP7CDW

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 2.1MHz
• Connectivity: SIO
• Peripherals: POR, Temp Sensor, WDT
• Number Of I /o: 22
• Program Memory Size: 6KB (6K x 8)
• Program Memory Type: OTP
• Ram Size: 224 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

PB0-PB7 — Port B Data Bits
7.3.2 Data Direction Register B
The contents of the port B data direction register (DDRB) determine whether each port B pin is an input
or an output. Writing a logic 1 to a DDRB bit enables the output buffer for the associated port B pin. A
DDRB bit set to a logic 1 also disables the pulldown device for that pin. Writing a logic 0 to a DDRB bit
disables the output buffer for the associated port B pin. A reset initializes all DDRB bits to logic 0s,
configuring all port B pins as inputs.
DDRB7–DDRB0 — Port B Data Direction Bits
7.3.3 Pulldown Register B
All port B pins can have software programmable pulldown devices enabled or disabled globally by the
SWPDI bit in the MOR. These pulldown devices are individually controlled by the write-only pulldown
register B (PDRB) shown in
devices if the port B pin is an input. Reading the PDRB returns undefined results since it is a write-only
register. Reset clears the PDIB7–PDIB0 bits, which turns on all the port B pulldown devices.
PDIB7–PDIB0 — Port B Pulldown Inhibit Bits
Freescale Semiconductor
These read/write bits are software programmable. Data direction of each bit is under the control of the
corresponding bit in data direction register B. Reset has no effect on port B data.
These read/write bits control port B data direction. Reset clears the bits DDRB7–DDRB0.
Writing to these write-only bits controls the port B pulldown devices. Reading these pulldown register
B bits returns undefined data. Reset clears bits PDIB7–PDIB0.
1 = Corresponding port B pin configured as output and pulldown device disabled
0 = Corresponding port B pin configured as input
1 = Corresponding port B pin pulldown device turned off
0 = Corresponding port B pin pulldown device turned on if pin has been programmed by the DDRB
to be an input
Address:
Address:
Reset:
Reset:
Read:
Read:
Write:
Write:
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
$0005
$0011
DDRB7
PDIB7
Bit 7
Bit 7
0
0
Figure
Figure 7-6. Data Direction Register B (DDRB)
Figure 7-7. Pulldown Register B (PDRB)
= Unimplemented
DDRB6
PDIB6
6
0
7-7. Clearing the PDIB7–PDIB0 bits in the PDRB turns on the pulldown
6
0
DDRB5
PDIB5
5
0
5
0
DDRB4
PDIB4
4
0
4
0
DDRB3
PDIB3
3
0
3
0
DDRB2
PDIB2
2
0
2
0
DDRB1
PDIB1
1
0
1
0
DDRB0
DIB0
Bit 0
Bit 0
0
0
Port B
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