MC68HC705JP7CDW Freescale Semiconductor, MC68HC705JP7CDW Datasheet - Page 109

• Manufacturer Part Number: MC68HC705JP7CDW
• Description: IC MCU 8BIT 28-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of MC68HC705JP7CDW

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 2.1MHz
• Connectivity: SIO
• Peripherals: POR, Temp Sensor, WDT
• Number Of I /o: 22
• Program Memory Size: 6KB (6K x 8)
• Program Memory Type: OTP
• Ram Size: 224 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

if multiple reads of the ACRH take place before the next read of the ACRL. Therefore, when reading the
MSB of the timer at ACRH, the LSB of the timer at ACRL must also be read to complete the read
sequence.
During power-on reset (POR), the counter is initialized to $FFFC and begins counting after the oscillator
startup delay. Because the counter is 16 bits and preceded by a fixed prescaler, the value in the counter
repeats every 262,144 internal bus clock cycles (524,288 oscillator cycles).
Reading the ACRH and ACRL in any order or any number of times does not have any effect on the 16-bit
free-running counter or the TOF flag bit.
11.4 Input Capture Registers
The input capture function is a means to record the time at which an event occurs. The source of the event
can be the change on an external pin (PB3/AN3/TCAP) or the CPF2 flag bit of voltage comparator 2 in
the analog subsystem. The ICEN bit in the analog subsystem control register (ACR) at $001D selects
which source is the input signal. When the input capture circuitry detects an active edge on the selected
source, it latches the contents of the free-running timer counter registers into the input capture registers
as shown in
Latching values into the input capture registers at successive edges of the same polarity measures the
period of the selected input signal. Latching the counter values at successive edges of opposite polarity
measures the pulse width of the signal.
Freescale Semiconductor
TCAP
AN3
PB3
RESET
Figure
SUBSYSTEM
ANALOG
To prevent interrupts from occurring between readings of the ACRH and
ACRL, set the I bit in the condition code register (CCR) before reading
ACRH and clear the I bit after reading ACRL.
Both the ICEN bit in the ACR and the IEDG bit in the TCR must be set when
using voltage comparator 2 to trigger the input capture function.
FROM
CONTROL
CPF2
FLAG
ICEN
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
BIT
BIT
11-6.
SELECT
READ
ICRH
INPUT
MUX
Figure 11-6. Timer Input Capture Block Diagram
& DETECT
SELECT
LOGIC
EDGE
$0012
TIMER CONTROL REG.
LATCH
NOTE
NOTE
ICRH ($0014)
INPUT CAPTURE (ICF)
16-BIT COUNTER
ICRL ($0015)
TIMER STATUS REG.
$0013
÷ 4
INTERNAL
INTERNAL
Input Capture Registers
DATA
DATA
BUS
BUS
INTERNAL
(OSC ÷ 2)
READ
INTERRUPT
ICRL
CLOCK
REQUEST
TIMER
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