MC68HC705JP7CDW Freescale Semiconductor, MC68HC705JP7CDW Datasheet - Page 112

• Manufacturer Part Number: MC68HC705JP7CDW
• Description: IC MCU 8BIT 28-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of MC68HC705JP7CDW

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 2.1MHz
• Connectivity: SIO
• Peripherals: POR, Temp Sensor, WDT
• Number Of I /o: 22
• Program Memory Size: 6KB (6K x 8)
• Program Memory Type: OTP
• Ram Size: 224 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Programmable Timer
11.6 Timer Control Register
The timer control register (TCR) shown in
Reset clears all the bits in the TCR with the exception of the IEDG bit which is unaffected.
ICIE — Input Capture Interrupt Enable Bit
OCIE — Output Compare Interrupt Enable Bit
TOIE — Timer Overflow Interrupt Enable
112
•
•
•
•
•
This read/write bit enables interrupts caused by an active signal on the TCAP pin or from CPF2 flag
bit of the analog subsystem voltage comparator 2. Reset clears the ICIE bit.
This read/write bit enables interrupts caused by an active match of the output compare function. Reset
clears the OCIE bit.
This read/write bit enables interrupts caused by a timer overflow. Reset clears the TOIE bit.
1 = Input capture interrupts enabled
0 = Input capture interrupts disabled
1 = Output compare interrupts enabled
0 = Output compare interrupts disabled
1 = Timer overflow interrupts enabled
0 = Timer overflow interrupts disabled
Enables input capture interrupts
Enables output compare interrupts
Enables timer overflow interrupts
Controls the active edge polarity of the TCAP signal
Controls the active level of the TCMP output
9B
...
...
B7
B6
BF
...
...
9A
Address:
Reset:
Read:
Write:
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
16
13
17
$0012
Bit 7
ICIE
0
Table 11-1. Output Compare Initialization Example
Figure 11-10. Timer Control Register (TCR)
SEI
...
...
STA
LDA
STX
...
...
CLI
= Unimplemented
OCIE
6
0
OCRH
TSR
OCRL
TOIE
Figure
5
0
DISABLE INTERRUPTS
.....
.....
INHIBIT OUTPUT COMPARE
ARM OCF FLAG FOR CLEARING
READY FOR NEXT COMPARE, OCF CLEARED
.....
.....
ENABLE INTERRUPTS
11-10, performs the following functions:
4
0
0
U = Unaffected
3
0
0
2
0
0
IEDG
U
1
Freescale Semiconductor
OLVL
Bit 0
0