MC68HC705JP7CDW Freescale Semiconductor, MC68HC705JP7CDW Datasheet - Page 116

• Manufacturer Part Number: MC68HC705JP7CDW
• Description: IC MCU 8BIT 28-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of MC68HC705JP7CDW

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 2.1MHz
• Connectivity: SIO
• Peripherals: POR, Temp Sensor, WDT
• Number Of I /o: 22
• Program Memory Size: 6KB (6K x 8)
• Program Memory Type: OTP
• Ram Size: 224 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Personality EPROM (PEPROM)
12.2 PEPROM Registers
Two I/O registers control programming and reading of the PEPROM:
12.2.1 PEPROM Bit Select Register
The PEPROM bit select register (PEBSR) selects one of 64 bits in the PEPROM array. Reset clears all
the bits in the PEPROM bit select register.
PEB7 and PEB6 — Not connected to the PEPROM array
PEB5–PEB0 — PEPROM Bit Selects
12.2.2 PEPROM Status and Control Register
The PEPROM status and control register (PESCR) controls the PEPROM programming voltage. This
register also transfers the PEPROM bits to the internal data bus and contains a flag bit when row zero is
selected.
PEDATA — PEPROM Data Bit
116
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•
These read/write bits are available as storage locations. Reset clears PEB7 and PEB6.
These read/write bits select one of 64 bits in the PEPROM as shown in
the PEPROM row, and bits PEB5–PEB3 select the PEPROM column. Reset clears PEB5–PEB0,
selecting the PEPROM bit in row zero, column zero.
This read-only bit is the output state of the PEPROM sense amplifier and shows the state of the
currently selected bit. The state of the PEDATA bit does not affect the programming of the bit selected
by the PEBSR. Reset does not affect the PEDATA bit.
1 = PEPROM data is a logic 1.
0 = PEPROM data is a logic 0.
The PEPROM bit select register (PEBSR)
The PEPROM status and control register (PESCR)
Address:
Address:
Reset:
Reset:
Read:
Write:
Read:
Write:
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Figure 12-3. PEPROM Status and Control Register (PESCR)
PEDATA
$000F
$000E
PEB7
Bit 7
Bit 7
U
0
Figure 12-2. PEPROM Bit Select Register (PEBSR)
= Unimplemented
PEB6
6
0
6
0
0
PEPGM
PEB5
5
0
5
0
PEB4
R
4
0
4
0
0
= Reserved
PEB3
R
3
0
3
0
0
PEB2
R
2
0
2
0
0
Table
U = Unaffected
PEB1
R
1
0
1
0
0
12-1. Bits PEB2–0 select
Freescale Semiconductor
PEPRZF
PEB0
Bit 0
Bit 0
0
1