MC68HC705JP7CDW Freescale Semiconductor, MC68HC705JP7CDW Datasheet - Page 80

• Manufacturer Part Number: MC68HC705JP7CDW
• Description: IC MCU 8BIT 28-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of MC68HC705JP7CDW

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 2.1MHz
• Connectivity: SIO
• Peripherals: POR, Temp Sensor, WDT
• Number Of I /o: 22
• Program Memory Size: 6KB (6K x 8)
• Program Memory Type: OTP
• Ram Size: 224 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Analog Subsystem
CPFR2
CPFR1
VOFF
COE1
CMP2
80
Writing a logic 1 to this write-only flag clears the CPF2 flag in the ASR. Writing a logic 0 to this bit has
no effect. Reading the CPFR2 bit will return a logic 0. By default, this bit looks cleared following a reset
of the device.
Writing a logic 1 to this write-only flag clears the CPF1 flag in the ASR. Writing a logic 0 to this bit has
no effect. Reading the CPFR1 bit will return a logic 0. By default, this bit looks cleared after a reset of
the device.
This read-write bit controls the addition of an offset voltage to the bottom of the sample capacitor. It is
not active unless the OPT bit in the COPR at location $1FF0 is set. Any reads of the VOFF bit location
return a logic 0 if the OPT bit is clear. During the time that the sample capacitor is connected to an
input (either HOLD or DHOLD set), the bottom of the sample capacitor is connected to V
bit is cleared by a reset of the device. For more information, see
This read-write bit controls the output of comparator 1 to the PB4 pin. It is not active unless the OPT
bit in the COPR at location $1FF0 is set. Any reads of the COE1 bit location return a logic 0 if the OPT
bit is clear. The COE1 bit is cleared by a reset of the device.
This read-only bit shows the state of comparator 2 during the time that the bit is read. This bit is
therefore the current state of the comparator without any latched history. The CMP2 bit will be high if
the voltage on the PB0/AN0 pin is greater than the voltage on the PB1/AN1 pin, regardless of the state
of the INV bit in the AMUX register. Since a reset disables comparator 2, this bit returns a logic 0
following a reset of the device.
1 = Clears the CPF2 flag bit
0 = No effect
1 = Clears the CPF1 flag bit
0 = No effect
1 = Enables approximately 100 mV offset to be added to the sample voltage when both the HOLD
0 = Connects the bottom of the sample capacitor to V
1 = Enables the output of comparator 1 to be ORed with the PB4 data bit and OLVL bit, if the DDRB4
0 = Disables the output of comparator 1 from affecting the PB4 pin
1 = The voltage on the positive input on comparator 2 is higher than the voltage on the negative
0 = The voltage on the positive input on comparator 2 is lower than the voltage on the negative input
and DHOLD control bits are cleared
bit is also set
input of comparator 2.
of comparator 2.
The CPFR1 and CPFR2 bits should be written with logic 1s following a
power-up of either comparator. This will clear out any latched CPF1 or
CPF2 flag bits which might have been set during the slower power-up
sequence of the analog circuitry.
If both inputs to a comparator are above the maximum common-mode input
voltage (V
may set the comparator flag. Applying a reset to the device may only
temporarily clear this flag as long as both inputs of a comparator remain
above the maximum common-mode input voltages.
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
DD
–1.5 V), the output of the comparator is indeterminate and
NOTE
SS
8.10 Sample and
Freescale Semiconductor
Hold.
SS
. The VOFF