MC68HC705JP7CDW Freescale Semiconductor, MC68HC705JP7CDW Datasheet - Page 78

• Manufacturer Part Number: MC68HC705JP7CDW
• Description: IC MCU 8BIT 28-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of MC68HC705JP7CDW

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 2.1MHz
• Connectivity: SIO
• Peripherals: POR, Temp Sensor, WDT
• Number Of I /o: 22
• Program Memory Size: 6KB (6K x 8)
• Program Memory Type: OTP
• Ram Size: 224 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Analog Subsystem
ICEN
CPIE
CP2EN
CP1EN
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This is a read/write bit that enables a voltage comparison to trigger the input capture register of the
programmable timer when the CPF2 flag bit is set. Therefore, an A/D conversion could be started by
receiving an OCF or TOF from the programmable timer and then terminated when the voltage on the
external ramping capacitor reaches the level of the unknown voltage. The time of termination will be
stored in the 16-bit buffer located at $0014 and $0015. This bit is automatically set whenever mode 2
or 3 is selected by setting the ATD2 control bit. This bit is cleared by a reset of the device.
This is a read/write bit that enables an analog interrupt when either of the CPF1 or CPF2 flag bits is
set to a logic 1. This bit is cleared by a reset of the device.
The CP2EN enable bit controls power to voltage comparator 2 in the analog subsystem. Powering
down a comparator will drop the supply current. This bit is cleared by a reset of the device.
The CP1EN enable bit will power down the voltage comparator 1 in the analog subsystem. Powering
down a comparator will drop the supply current. This bit is cleared by a reset of the device.
1 = Connects the CPF2 flag bit to the timer input capture register
0 = Connects the PB3/AN3 pin to the timer input capture register
1 = Enables analog interrupts when comparator flag bits are set
0 = Disables analog interrupts when comparator flag bits are set
1 = Writing a logic 1 powers up voltage comparator 2.
0 = Writing a logic 0 powers down voltage comparator 2.
1 = Writing a logic 1 powers up voltage comparator 1
0 = Writing a logic 0 powers down voltage comparator 1
For the input capture to occur when the output of comparator 2 goes high,
the IEDG bit in the TCR must also be set.
When the ICEN bit is set, the input capture function of the programmable
timer is not connected to the PB3/AN3/TCAP pin but is driven by the CPF2
output flag from comparator 2. To return to capturing times from external
events, the ICEN bit must first be cleared before the timed event occurs.
If both the ICEN and CPIE bits are set, they will both generate an interrupt
by different paths. One will be the programmable timer interrupt due to the
input capture and the other will be the analog interrupt due to the output of
comparator 2 going high. In this case, the input capture interrupt will be
entered first due to its higher priority. The analog interrupt will then need to
be serviced even if the comparator 2 output has been reset or the input
capture flag (ICF) has been cleared.
Voltage comparators power up slower than digital logic and their outputs
may go through indeterminate states which might set their respective flags
(CPF1, CPF2). It is therefore recommended to power up the charge current
source first (ISEN), then to power up any comparators, and finally clear the
flag bits by writing a logic 1 to the respective CPFR1 or CPFR2 bits in the
ACR.
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
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Freescale Semiconductor