MC68HC908BD48IFB Freescale Semiconductor, MC68HC908BD48IFB Datasheet - Page 167

• Manufacturer Part Number: MC68HC908BD48IFB
• Description: IC MCU 48K FLASH 6MHZ USB 44PQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908BD48IFB

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 6MHz
• Connectivity: I²C, USB
• Peripherals: POR, PWM
• Number Of I /o: 32
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 44-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

MC68HC908BD48
Freescale Semiconductor
—
Rev. 2.1
TBEF — Transmit Buffer Empty Flag
RBFF — Receive Buffer Full Flag
EOPIF — End Of Packet Interrupt Flag
RSTIF — Reset Interrupt Flag
This flag is set after the data stored in endpoint 0 transmit buffer has
been sent and ACK handshake packet is received. Software must
clear this flag by writing a logic "1" to TBEFR bit after the data is ready
in the transmit buffer. This enables the next data packet transmission
when endpoint 0 transmit is enabled (TX0E = 1). TBEF generates an
interrupt request to the CPU if the TBIE bit is also set. Reset clears
this bit.
This flag is set when the module has received one data packet and
replied with ACK handshake packet. Software must clear this flag by
writing "1" to RBFFR bit after all the received data have been read to
enable the next data packet reception. RBFF generates an interrupt
request to the CPU if the RBIE bit is also set. Reset clears this bit.
This flag is set when a valid EOP signal transition is detected on the
D+ and D– lines. This flag can be cleared by writing "1" to EOPIFR bit.
EOPIF generates an interrupt request to the CPU if the EOPIE bit is
also set. Reset clears this bit.
The flag is set when a valid reset signal state is detected on the D+
and D– lines. This flag can be cleared by writing "1" to RSTIFR bit.
RSTIF generates an interrupt request to the CPU if the RSTIE bit is
also set. Reset clears this bit.
1 = Transmit on endpoint 0 has occurred
0 = Transmit on endpoint 0 has not occurred
1 = Receive on endpoint 0 has occurred
0 = Receive on endpoint 0 has not occurred
1 = End-of-packet sequence has been detected
0 = End-of-packet sequence has not been detected
1 = USB reset condition has been detected
0 = USB reset condition has not been detected
Universal Serial Bus Module (USB)
Universal Serial Bus Module (USB)
Data Sheet
167