MC68HC908BD48IFB Freescale Semiconductor, MC68HC908BD48IFB Datasheet - Page 202

no-image

MC68HC908BD48IFB

Manufacturer Part Number
MC68HC908BD48IFB
Description
IC MCU 48K FLASH 6MHZ USB 44PQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC68HC908BD48IFB

Core Processor
HC08
Core Size
8-Bit
Speed
6MHz
Connectivity
I²C, USB
Peripherals
POR, PWM
Number Of I /o
32
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 6x8b
Oscillator Type
Internal
Operating Temperature
0°C ~ 85°C
Package / Case
44-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68HC908BD48IFB
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
DDC12AB Interface
15.6.5 DDC Status Register (DSR)
Data Sheet
202
Address:
RXIF — DDC Receive Interrupt Flag
TXIF — DDC Transmit Interrupt Flag
MATCH — DDC Address Match
Reset:
Read:
Write:
This flag is set after the data receive register (DDRR) is loaded with a
new received data. Once the DDRR is loaded with received data, no
more received data can be loaded to the DDRR register until the CPU
reads the data from the DDRR to clear RXBF flag. RXIF generates an
interrupt request to CPU if the DIEN bit in DCR is also set. This bit is
cleared by writing "0" to it or by reset; or when the DEN = 0.
This flag is set when data in the data transmit register (DDTR) is
downloaded to the output circuit, and that new data can be written to
the DDTR. TXIF generates an interrupt request to CPU if the DIEN bit
in DCR is also set. This bit is cleared by writing "0" to it or when the
DEN = 0.
This flag is set when the received data in the data receive register
(DDRR) is an calling address which matches with the address or its
extended addresses (EXTAD=1) specified in the DADR register.
1 = New data in data receive register (DDRR)
0 = No data received
1 = Data transfer completed
0 = Data transfer in progress
1 = Received address matches DADR
0 = Received address does not match
$0019
RXIF
Bit 7
0
0
Figure 15-5. DDC Status Register (DSR)
= Unimplemented
DDC12AB Interface
TXIF
6
0
0
MATCH
5
0
SRW
4
0
RXAK
3
1
MC68HC908BD48
SCLIF
Freescale Semiconductor
2
0
0
TXBE
1
1
Rev. 2.1
RXBF
Bit 0
0

Related parts for MC68HC908BD48IFB