MC68HC908BD48IFB Freescale Semiconductor, MC68HC908BD48IFB Datasheet - Page 183

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MC68HC908BD48IFB

Manufacturer Part Number
MC68HC908BD48IFB
Description
IC MCU 48K FLASH 6MHZ USB 44PQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC68HC908BD48IFB

Core Processor
HC08
Core Size
8-Bit
Speed
6MHz
Connectivity
I²C, USB
Peripherals
POR, PWM
Number Of I /o
32
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 6x8b
Oscillator Type
Internal
Operating Temperature
0°C ~ 85°C
Package / Case
44-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68HC908BD48IFB
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
14.5.2 Multi-Master IIC Control Register (MMCR)
MC68HC908BD48
Freescale Semiconductor
Rev. 2.1
Address:
MMEN — Multi-Master IIC Enable
MMIEN — Multi-Master IIC Interrupt Enable
MMTXAK — Transmit Acknowledge Enable
Reset:
Read:
Write:
This bit is set to enable the Multi-master IIC module. When
MMEN = 0, module is disabled and all flags will restore to its power-
on default states. Reset clears this bit.
When this bit is set, the MMTXIF, MMRXIF, MMALIF, and MMNAKIF
flags are enabled to generate an interrupt request to the CPU. When
MMIEN is cleared, the these flags are prevented from generating an
interrupt request. Reset clears this bit.
This bit is set to disable the MMIIC from sending out an acknowledge
signal to the bus at the 9th clock bit after receiving 8 data bits. When
MMTXAK is cleared, an acknowledge signal will be sent at the 9th
clock bit. Reset clears this bit.
1 = MMIIC module enabled
0 = MMIIC module disabled
1 = MMTXIF, MMRXIF, MMALIF, and/or MMNAKIF bit set will
0 = MMTXIF, MMRXIF, MMALIF, and/or MMNAKIF bit set will not
1 = MMIIC does not send acknowledge signals at 9th clock bit
0 = MMIIC sends acknowledge signal at 9th clock bit
Figure 14-2. Multi-Master IIC Control Register (MMCR)
MMEN
$004C
Bit 7
generate interrupt request to CPU
generate interrupt request to CPU
Multi-Master IIC Interface (MMIIC)
0
= Unimplemented
MMIEN
6
0
5
0
0
4
0
0
MMTXAK
3
0
Multi-Master IIC Interface (MMIIC)
2
0
0
1
0
0
Data Sheet
Bit 0
0
0
183

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