MC68HC908BD48IFB Freescale Semiconductor, MC68HC908BD48IFB Datasheet - Page 215

• Manufacturer Part Number: MC68HC908BD48IFB
• Description: IC MCU 48K FLASH 6MHZ USB 44PQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908BD48IFB

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 6MHz
• Connectivity: I²C, USB
• Peripherals: POR, PWM
• Number Of I /o: 32
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 44-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

16.5.2 Sync Signal Counters
16.5.3 Polarity Controlled HSYNCO and VSYNCO Outputs
MC68HC908BD48
Freescale Semiconductor
—
Rev. 2.1
There are two counters: a 13-bit horizontal frequency counter to count
the number of horizontal sync pulses within a 32ms or 8ms period; and
a 13-bit vertical frequency counter to count the number of system clock
cycles between two vertical sync pulses. These two data can be read by
the CPU to check the signal frequencies and to determine the video
mode.
The 13-bit vertical frequency register encompasses vertical frequency
range from approximately 15Hz to 128kHz. Due to the asynchronous
timing between the incoming VSYNC signal and internal system clock,
there will be ±1 count error on reading the
Registers (VFRs)
The horizontal counter counts the pulses on HSYNC pin input, and is
uploaded to the
or 8.192ms.
The processed sync signals are output on HSYNCO and VSYNCO when
the corresponding bits in Configuration Register 0 ($001D) are set. The
signal to these output pins depend on SOUT and COMP bits (see
16-3), with polarity controlled by ATPOL, HINVO, and VINVO bits as
shown in
SOUT
1
0
0
Table
COMP
X
0
1
Hsync Frequency Registers (HFRs)
16-4.
Sync Processor
Table 16-3. Sync Output Control
for the same vertical frequency.
Free-running pulse with negative polarity
Sync outputs follow sync inputs VSYNC and HSYNC
respectively, with polarity correction shown in
HSYNCO follows the composite sync input and VSYNCO
is the extracted Vsync (3 to 14µs delay to composite
input), with polarity correction shown in
VSYNCO and HSYNCO
Sync Outputs:
Vertical Frequency
every 32.768ms
Table
Sync Processor
Table
16-4.
Data Sheet
Table
16-4.
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