MC68HC908BD48IFB Freescale Semiconductor, MC68HC908BD48IFB Datasheet - Page 194

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MC68HC908BD48IFB

Manufacturer Part Number
MC68HC908BD48IFB
Description
IC MCU 48K FLASH 6MHZ USB 44PQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC68HC908BD48IFB

Core Processor
HC08
Core Size
8-Bit
Speed
6MHz
Connectivity
I²C, USB
Peripherals
POR, PWM
Number Of I /o
32
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 6x8b
Oscillator Type
Internal
Operating Temperature
0°C ~ 85°C
Package / Case
44-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68HC908BD48IFB
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
DDC12AB Interface
15.3 Features
15.4 I/O Pins
Data Sheet
194
Generic Pin Names:
DDC12AB
SDA
SCL
This DDC12AB module uses the DDCSCL clock line and the DDCSDA
data line to communicate with external DDC host or IIC interface. These
two pins are shared with port pins PTD3 and PTD2 respectively. The
outputs of DDCSDA and DDCSCL pins are open-drain type — no
clamping diode is connected between the pin and internal V
maximum data rate typically is 100k-bps. The maximum communication
length and the number of devices that can be connected are limited by
a maximum bus capacitance of 400pF.
The DDC12AB module uses two I/O pins, shared with standard port I/O
pins. The full name of the DDC12AB I/O pins are listed in
The generic pin name appear in the text that follows.
Table 15-1. Pin Name Conventions
DDC1 hardware
Compatibility with multi-master IIC bus standard
Software controllable acknowledge bit generation
Interrupt driven byte by byte data transfer
Calling address identification interrupt
Auto detection of R/W bit and switching of transmit or receive
mode
Detection of START, repeated START, and STOP signals
Auto generation of START and STOP condition in master mode
Arbitration loss detection and No-ACK awareness in master mode
8 selectable baud rate master clocks
Automatic recognition of the received acknowledge bit
Full MCU Pin Names:
PTD2/DDCSDA
PTD3/DDCSCL
DDC12AB Interface
DDCSCLE bit in PDCR ($0049)
DDCDATE bit in PDCR ($0049)
DDC Function By:
Pin Selected for
MC68HC908BD48
Freescale Semiconductor
Table
DD
. The
15-1.
Rev. 2.1

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