MC68HC908BD48IFB Freescale Semiconductor, MC68HC908BD48IFB Datasheet - Page 243

• Manufacturer Part Number: MC68HC908BD48IFB
• Description: IC MCU 48K FLASH 6MHZ USB 44PQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908BD48IFB

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 6MHz
• Connectivity: I²C, USB
• Peripherals: POR, PWM
• Number Of I /o: 32
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 44-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

17.6.2 Data Direction Register D
MC68HC908BD48
Freescale Semiconductor
—
Rev. 2.1
Address:
CLAMP — Sync Processor Clamp pulse output pin
DDCSCL, DDCSDA — DDC12AB Data and Clock pins
D–, D+ — USB I/O pins
Data direction register D (DDRD) determines whether each port D pin is
an input or an output. Writing a logic 1 to a DDRD bit enables the output
buffer for the corresponding port D pin; a logic 0 disables the output
buffer.
DDRD6–DDRD0 — Data Direction Register D Bits
Reset:
Read:
Write:
The PTD4/CLAMP pin is the sync processor clamp pulse output pin.
When the CLAMPE bit in the port D configuration register (PDCR) is
clear, the PTD4/CLAMP pin is available for general-purpose I/O. See
17.6.3 Port D
The PTD3/DDCSCL and PTD2/DDCSDA pins are DDC12AB clock
and data pins respectively. When the DDCSCLE and DDCDATE bits
in the port D configuration register (PDCR) is clear, the
PTD3/DDCSCL and PTD2/DDCSDA pins are available for general-
purpose I/O. See
The PTD1/D– and PTD0/D+ pins are the USB port pins. When the
USBD–E and USBD+E bits in the port D configuration register (PDCR)
is clear, the PTD1/D– and PTD0/D+ pins are available for general-
purpose I/O. See
These read/write bits control port D data direction. Reset clears
DDRD6–DDRD0, configuring all port D pins as inputs.
1 = Corresponding port D pin configured as output
0 = Corresponding port D pin configured as input
$0007
Bit 7
Figure 17-13. Data Direction Register D (DDRD)
0
0
Input/Output (I/O) Ports
DDRD6
Options.
6
0
17.6.3 Port D
17.6.3 Port D
DDRD5
5
0
DDRD4
Options.
Options.
4
0
DDRD3
3
0
DDRD2
2
0
Input/Output (I/O) Ports
DDRD1
1
0
Data Sheet
DDRD0
Bit 0
0
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