MC68HC908BD48IFB Freescale Semiconductor, MC68HC908BD48IFB Datasheet - Page 187

• Manufacturer Part Number: MC68HC908BD48IFB
• Description: IC MCU 48K FLASH 6MHZ USB 44PQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908BD48IFB

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 6MHz
• Connectivity: I²C, USB
• Peripherals: POR, PWM
• Number Of I /o: 32
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 44-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

MC68HC908BD48
Freescale Semiconductor
—
Rev. 2.1
MMTXIF — Multi-Master Transmit Interrupt Flag
MMATCH — Multi-Master Address Match
MMSRW — Multi-Master Slave Read/Write
MMRXAK — Multi-Master Receive Acknowledge
This flag is set when data in the data transmit register (MMDTR) is
downloaded to the output circuit, and that new data can be written to
the MMDTR. MMTXIF generates an interrupt request to CPU if the
MMIEN bit in MMCR is also set. This bit is cleared by writing "0" to it
or when the MMEN = 0.
This flag is set when the received data in the data receive register
(MMDRR) is an calling address which matches with the address or its
extended addresses (MMEXTAD=1) specified in the MMADR
register.
This bit indicates the data direction when the module is in slave mode.
It is updated after the calling address is received from a master
device. MMSRW = 1 when the calling master is reading data from the
module (slave transmit mode). MMSRW = 0 when the master is
writing data to the module (receive mode).
When this bit is cleared, it indicates an acknowledge signal has been
received after the completion of 8 data bits transmission on the bus.
When MMRXAK is set, it indicates no acknowledge signal has been
detected at the 9th clock; the module will release the SDA line for the
master to generate "stop" or "repeated start" condition. Reset sets this
bit.
1 = Data transfer completed
0 = Data transfer in progress
1 = Received address matches MMADR
0 = Received address does not match
1 = Slave mode transmit
0 = Slave mode receive
1 = No acknowledge signal received at 9th clock bit
0 = Acknowledge signal received at 9th clock bit
Multi-Master IIC Interface (MMIIC)
Multi-Master IIC Interface (MMIIC)
Data Sheet
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