DSP56303VL100 Freescale Semiconductor, DSP56303VL100 Datasheet

IC DSP 24BIT 100MHZ 196-MAPBGA

DSP56303VL100

Manufacturer Part Number
DSP56303VL100
Description
IC DSP 24BIT 100MHZ 196-MAPBGA
Manufacturer
Freescale Semiconductor
Series
DSP563xxr
Type
Fixed Pointr
Datasheet

Specifications of DSP56303VL100

Interface
Host Interface, SSI, SCI
Clock Rate
100MHz
Non-volatile Memory
ROM (576 B)
On-chip Ram
24kB
Voltage - I/o
3.30V
Voltage - Core
3.30V
Operating Temperature
-40°C ~ 100°C
Mounting Type
Surface Mount
Package / Case
196-MAPBGA
Device Core Size
24b
Format
Fixed Point
Clock Freq (max)
100MHz
Mips
100
Device Input Clock Speed
100MHz
Ram Size
24KB
Program Memory Size
Not RequiredKB
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
196
Package Type
MA-BGA
Package
196MA-BGA
Maximum Speed
100 MHz
Device Million Instructions Per Second
100 MIPS
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
© Freescale Semiconductor, Inc., 1996, 2005. All rights reserved.
Freescale Semiconductor
Technical Data
DSP56303
24-Bit Digital Signal Processor
The DSP56303 is a member of the DSP56300 core family of programmable CMOS DSPs. Significant architectural
features of the DSP56300 core family include a barrel shifter, 24-bit addressing, instruction cache, and DMA. The
DSP56303 offers 100 MMACS using an internal 100 MHz clock at 3.0–3.6 volts. The DSP56300 core family
offers a rich instruction set and low power dissipation, as well as increasing levels of speed and power to enable
wireless, telecommunications, and multimedia products.
EXTAL
PINIT/NMI
XTAL
RESET
Bootstrap
2
Internal
Generator
Timer
Six-Channel
Switch
Triple
Generation
DMA Unit
ROM
Data
Bus
Address
Clock
PLL
Unit
16
HI08
Controller
Program
Interrupt
6
ESSI
Expansion Area
6
MODA/IRQA
MODB/IRQB
MODC/IRQC
MODD/IRQD
Peripheral
Controller
Program
Decode
3
SCI
Figure 1. DSP56303 Block Diagram
Generator
Program
Address
4096 × 24
PrograM
(default)
RAM
bits
DSP56300
24-Bit
Core
DDB
YDB
XDB
PDB
GDB
DAB
YAB
XAB
PAB
24 × 24 + 56 → 56-bit MAC
Memory Expansion Area
Two 56-bit Accumulators
2048 × 24
56-bit Barrel Shifter
(default)
X Data
RAM
bits
Data ALU
2048 × 24
(default)
Y Data
RAM
bits
Data Bus
Interface
External
Address
External
and Inst.
External
Control
Switch
Cache
Switch
Management
Bus
Bus
OnCE™
Power
JTAG
Control
Address
Data
DE
18
13
24
5
The DSP56303 is intended
for use in telecommunication
applications, such as multi-
line voice/data/ fax
processing, video
conferencing, audio
applications, control, and
general digital signal
processing.
Rev. 11 includes the following
changes:
• Adds lead-free packaging and
part numbers.
What’s New?
Rev. 11, 2/2005
DSP56303

Related parts for DSP56303VL100

DSP56303VL100 Summary of contents

Page 1

... DSP56303 offers 100 MMACS using an internal 100 MHz clock at 3.0–3.6 volts. The DSP56300 core family offers a rich instruction set and low power dissipation, as well as increasing levels of speed and power to enable wireless, telecommunications, and multimedia products. © Freescale Semiconductor, Inc., 1996, 2005. All rights reserved. 3 Memory Expansion Area ...

Page 2

... Means that a high true (active high) signal is low or that a low true (active low) signal is high Examples: Signal/Symbol PIN PIN PIN PIN Note: Values for , , , and Logic State Signal State True Asserted False Deasserted True Asserted False Deasserted are defined by individual product specifications DSP56303 Technical Data, Rev. 11 pin is active when RESET Voltage Freescale Semiconductor ...

Page 3

... Optimized power management circuitry (instruction-dependent, peripheral-dependent, and mode- dependent) • 144-pin TQFP package in lead-free or lead-bearing versions Packaging • 196-pin molded array plastic-ball grid array (MAP-BGA) package in lead-free or lead-bearing versions Freescale Semiconductor Table 1. DSP56303 Features Description Instruction X Data RAM Y Data RAM ...

Page 4

... The documents listed in Table 2 are required for a complete description of the DSP56303 device and are necessary to design properly with the part. Documentation is available from a local Freescale distributor, a Freescale semiconductor sales office Freescale Semiconductor Literature Distribution Center. For documentation updates, visit the Freescale DSP website. See the contact information on the back cover of this document. ...

Page 5

... These are designated as no connect (NC) in the package description (see Chapter 3). Note: This chapter refers to a number of configuration registers used to select individual multiplexed signal functionality. Refer to the DSP56303 User’s Manual for details on these configuration registers. Freescale Semiconductor DSP56303 Functional Signal Groupings Functional Group DSP56303 Technical Data, Rev ...

Page 6

... PB9 HA9 PB10 HA10 PB13 Double DS HRD/HRD PB11 HWR/HWR PB12 Double HR HTRQ/HTRQ PB14 HRRQ/HRRQ PB15 Port C GPIO PC[0–2] PC3 PC4 PC5 Port D GPIO PD[0–2] PD3 PD4 PD5 Port E GPIO PE0 PE1 PE2 Timer GPIO TIO0 TIO1 TIO2 Freescale Semiconductor ...

Page 7

... Ground—Connected to an internal device ground plane. Notes: 1. The user must provide adequate external decoupling capacitors for all GND connections. 2. These connections are only used on the TQFP package. 3. These connections are common grounds used on the MAP-BGA package. Freescale Semiconductor Table 1-2. Power Inputs Description power rail CCQ ...

Page 8

... Otherwise, the signals are tri-stated. To minimize power dissipation, A[0–17] do not change state when external memory spaces are not being accessed. DSP56303 Technical Data, Rev. 11 Signal Description Signal Description CCP , GND, or left floating CAS Freescale Semiconductor . ...

Page 9

... BRH bit setting: • BRH = 0: Output, deasserted • BRH = 1: Maintains last state (that is, if asserted, remains asserted) Freescale Semiconductor Table 1-7. External Data Bus Signals State During Stop or Wait Last state: Data Bus—When the DSP is the bus master, D[0–23] are active-high, ...

Page 10

... Address Trace Enable bit is set. When BCLK is active and synchronized to CLKOUT by the internal PLL, BCLK precedes CLKOUT by one-fourth of a clock cycle. Bus Clock Not When the DSP is the bus master, BCLK is the inverse of the BCLK signal. Otherwise, the signal is tri-stated. DSP56303 Technical Data, Rev. 11 Freescale Semiconductor ...

Page 11

... Schmitt-trigger Input Input IRQD Note: These signals are all 5 V tolerant. Freescale Semiconductor Table 1-9. Interrupt and Mode Control Reset Reset—Places the chip in the Reset state and resets the internal phase generator. The Schmitt-trigger input allows a slowly rising input (such as a capacitor charging) to reset the chip reliably ...

Page 12

... HI function is selected, these signals are lines 0–7 of the bidirectional multiplexed Address/Data bus. Port B 0–7—When the HI08 is configured as GPIO through the HI08 Port Control Register, these signals are individually programmed as inputs or outputs through the HI08 Data Direction Register. DSP56303 Technical Data, Rev. 11 Signal Description Freescale Semiconductor ...

Page 13

... PB13 Input or Output HRW Input HRD/HRD Input PB11 Input or Output Freescale Semiconductor Table 1-11. Host Interface (Continued) 1,2 Reset Ignored Input Host Address Input 0—When the HI08 is programmed to interface with a nonmultiplexed host bus and the HI function is selected, this signal is line 0 of the host address input bus. Host Address Strobe— ...

Page 14

... Port B 15—When the HI08 is configured as GPIO through the HI08 Port Control Register, this signal is individually programmed as an input or output through the HI08 Data Direction Register. DSP56303 Technical Data, Rev. 11 Signal Description Freescale Semiconductor ...

Page 15

... Input/Output PC3 Input or Output SRD0 Input PC4 Input or Output Freescale Semiconductor Enhanced Synchronous Serial Interface 0 (ESSI0) Enhanced Synchronous Serial Interface 0 1,2 Reset Ignored Input Serial Control 0—For asynchronous mode, this signal is used for the receive clock I/O (Schmitt-trigger input). For synchronous mode, this signal is used either for transmitter 1 output or for serial I/O flag 0. Port C 0— ...

Page 16

... Port D 2—The default configuration following reset is GPIO input PD2. When configured as PD2, signal direction is controlled through the Port D Direction Register. The signal can be configured as an ESSI signal SC12 through the Port D Control Register. DSP56303 Technical Data, Rev. 11 Signal Description Signal Description Freescale Semiconductor ...

Page 17

... If the last state is input, the signal is an ignored input. • If the last state is output, the signal is tri-stated. 2. The Wait processing state does not affect the signal state. 3. All inputs are 5 V tolerant. Freescale Semiconductor Enhanced Synchronous Serial Interface 1 (ESSI1) Enhanced Serial Synchronous Interface 1 (Continued) 1,2 Reset Ignored Input Serial Clock— ...

Page 18

... Port E 2—The default configuration following reset is GPIO input PE2. When configured as PE2, signal direction is controlled through the Port E Direction Register. The signal can be configured as an SCI signal SCLK through the Port E Control Register. DSP56303 Technical Data, Rev. 11 Signal Description Freescale Semiconductor ...

Page 19

... If the last state is input, the signal is an ignored input. • If the last state is output, the signal is tri-stated. 2. The Wait processing state does not affect the signal state. 3. All inputs are 5 V tolerant. Freescale Semiconductor Table 1-15. Triple Timer Signals 1,2 Reset Timer 0 Schmitt-Trigger Input/Output— When Timer 0 functions as an external event counter or in measurement mode, TIO0 is used as input ...

Page 20

... OnCE module to initiate debug mode directly or to provide a direct external indication that the chip has entered Debug mode. All other interface with the OnCE module must occur through the JTAG port. DSP56303 Technical Data, Rev. 11 Signal Description Freescale Semiconductor ...

Page 21

... Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond the maximum rating may affect device reliability or cause permanent damage to the device power-up, ensure that the voltage difference between the 5 V tolerant pins and the chip V Freescale Semiconductor CAUTION Table 2-1. Absolute Maximum Ratings ...

Page 22

... V – 0.01 — — CC — — 0.4 — — 0.01 — 127 — — 7.5 — — 100 — — 1 2.5 — — 10 Freescale Semiconductor Unit ° C/W ° C/W ° C/W Unit µA µ µ ...

Page 23

... With PLL disabled With PLL enabled and MF ≤ 4 • • With PLL enabled and MF > 4 Internal clock and CLKOUT cycle time with PLL enabled Freescale Semiconductor 6 DC Electrical Characteristics Symbol = the high V value may cause additional power consumption (DC current). To minimize ...

Page 24

... Figure 2-1. Crystal Oscillator Circuits . CLKOUT Midpoint Figure 2-2. External Clock Timing DSP56303 Technical Data, Rev Expression Typ Max 2 × ET — — MHz OSC R = 680 kΩ ± 10 ± 20% V IHX Note: The midpoint is 0 IHX ILX 5 7 Freescale Semiconductor ...

Page 25

... Voltage Controlled Oscillator (VCO) frequency when PLL enabled (MF × E × 2/PDF) f PLL external capacitor (PCAP pin CCP @ MF ≤ 4 • • > 4 Note the value of the PLL capacitor (connected between the PCAP pin and V PCAP listed above. Freescale Semiconductor Table 2-5. Clock Operation Table 2-6. PLL Characteristics 1 ) PCAP (580 × ...

Page 26

... C + 2.0 74.5 — 5.0 105.0 — – 10.94 — Note – 10.94 — Note – 10.94 — Note – 10.94 — Note – 10.94 — Note – 10.94 — Note 5 1.0 83.5 — 5.0 — 252 Freescale Semiconductor ...

Page 27

... Data write to HI08, ESSI, SCI • Timer • IRQ, NMI (edge trigger) 29 Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to external memory (DMA source) access address out valid Freescale Semiconductor Expression PLC × ET × PDF + (128 K − C PLC/2) × T PLC × ET × PDF + (23.75 ± ...

Page 28

... T is not constant, and their width may vary, so timing may vary pF Reset Value Figure 2-3. Reset Timing DSP56303 Technical Data, Rev (Continued) 100 MHz Expression Min Max is valid, and the EXTAL input valid. The specified timing First Fetch Freescale Semiconductor Unit ...

Page 29

... RESET A[0–17] A[0–17 IRQA, IRQB, IRQC, IRQD, NMI General Purpose I/O IRQA, IRQB, IRQC, IRQD, NMI Freescale Semiconductor 12 Figure 2-4. Synchronous Reset Timing First Interrupt Instruction Execution/Fetch First Interrupt Instruction Execution 18 b) General-Purpose I/O Figure 2-5. External Fast Interrupt Timing DSP56303 Technical Data, Rev ...

Page 30

... IRQC, IRQD, NMI A[0–17] Figure 2-7. RESET MODA, MODB, MODC, MODD, PINIT Figure 2-8. 2- External Interrupt Timing (Negative Edge-Triggered) 22 Synchronous Interrupt from Wait State Timing Operating Mode Select Timing DSP56303 Technical Data, Rev IRQA, IRQB, IRQC, IRQD, NMI IL Freescale Semiconductor ...

Page 31

... IRQA A[0–17] Figure 2-10. A[0–17 IRQA, IRQB, IRQC, IRQD, NMI Figure 2-11. Freescale Semiconductor 24 25 Recovery from Stop State Using IRQA 26 25 Recovery from Stop State Using IRQA Interrupt Service DMA Source Address 29 First Interrupt Instruction Execution External Memory Access (DMA Source) Timing DSP56303 Technical Data, Rev ...

Page 32

... C – 5.0 — 7 0.0 — ns − 4.0 13.5 — − 3.0 4.5 — − 2.0 0.5 — − 2.0 10.5 — − 2.0 20.5 — − 3.7 3.8 — – 3.7 –1.2 — − 3.7 –6.2 — Freescale Semiconductor ...

Page 33

... All timings for 100 MHz are measured from 0.5 × Vcc to 0.5 × Vcc Timing 118 is relative to the deassertion edge even if TA remains asserted. = 3.3 V ± 0 –40°C to +100° Freescale Semiconductor SRAM Read and Write Accesses (Continued) Symbol Expression 0.25 × T — [1 ≤ WS ≤ 3] 1.25 × 0.2 [4 ≤ WS ≤ 7] 2.25 × T 1.25 × ...

Page 34

... Figure 2-12. SRAM Read Access 100 107 101 102 114 108 Figure 2-13. SRAM Write Access DSP56303 Technical Data, Rev. 11 117 106 118 119 Data In 103 119 118 109 Data Out Freescale Semiconductor ...

Page 35

... DRAM type (tRAC ns) 100 Figure 2-14. Freescale Semiconductor Note: This figure should be used for primary selection. For exact and detailed timings, see the following tables 100 1 Wait states 3 Wait states ...

Page 36

... T − 4.0 21.0 — 1.25 × T − 4.3 8.2 — 3.5 × T − 4.0 31.0 — 2.5 × T − 5.7 — 19 0.0 — ns 0.75 × T – 1.5 6.0 — 0.25 × T — 2 equals 4 × PC and not t . OFF GZ Freescale Semiconductor ...

Page 37

... BRW[1–0] (DRAM control register bits) defines the number of wait states that should be inserted in each DRAM out-of-page access deassertion always occurs after CAS deassertion; therefore, the restricted timing is t Freescale Semiconductor DRAM Page Mode Timings, Four Wait States Symbol ...

Page 38

... Address 143 132 133 153 154 Data In Data In DRAM Page Mode Read Accesses DSP56303 Technical Data, Rev. 11 136 135 138 142 Last Column Address 147 148 156 Data Out 136 135 138 142 Last Column Address 152 134 Data In Freescale Semiconductor ...

Page 39

... RAS assertion to column address valid 169 CAS deassertion to RAS assertion 170 CAS deassertion pulse width 171 Row address valid to RAS assertion Freescale Semiconductor Note: This figure should be used for primary selection. For exact and detailed timings, see the following tables. 120 40 66 ...

Page 40

... C 1.5 × T − 4.0 11.0 — 2.75 × T − 4.0 23.5 — 11.5 × T − 4.0 111.0 — × T − 7.0 — 93 0.0 — ns 0.75 × T – 1.5 6.0 — 0.25 × T — 2 and not t . OFF GZ Freescale Semiconductor ...

Page 41

... The refresh period is specified in the DRAM Control Register. Use the expression to compute the maximum or minimum value listed (or both if the expression includes ± Either must be satisfied for read cycles. RCH RRH 5. RD deassertion always occurs after CAS deassertion; therefore, the restricted timing is t Freescale Semiconductor Symbol RAC t CAC ...

Page 42

... Row Address Column Address 172 176 177 191 160 159 158 192 DRAM Out-of-Page Read Access DSP56303 Technical Data, Rev. 11 162 164 174 179 178 193 161 Data In Freescale Semiconductor ...

Page 43

... RAS CAS A[0–17 D[0–23] Figure 2-19. RAS CAS WR Freescale Semiconductor 162 163 165 167 169 168 170 173 171 172 Row Address 181 188 182 184 183 187 185 194 DRAM Out-of-Page Write Access 157 162 163 190 170 ...

Page 44

... DSP56303 Technical Data, Rev. 11 1,2 100 MHz 3,4,5 Unit Min Max — 6.5 ns 2.5 — ns 4.0 — ns 0.0 — ns 2.5 — ns — 6.5 ns 2.5 — ns — 2.5 ns 4.0 — ns 0.0 — 2.5 6.7 10 0.0 4 4.3 5.0 9 0.0 4.3 ns 0.0 3.8 ns Freescale Semiconductor ...

Page 45

... D[0–23] 208 RD D[0–23] Note: Address lines A[0–17] hold their state after a read or write operation. AA[0–3] do not hold their state after a read or write operation. Figure 2-22. Freescale Semiconductor 198 210 203 Data Out 208 202 206 Synchronous Bus Timings 1 WS (BCR Controlled) ...

Page 46

... T maximum: 0.25 × T 0.75 × T DSP56303 Technical Data, Rev 100 MHz 2 Unit Min Max 0.0 4.0 ns 4.0 — ns 0.0 — ns 4.0 — ns 0.0 — ns 0.0 4.0 ns 0.0 4.0 ns — 4.5 ns 2.5 — — 7 2.5 — 4.0 2.0 6 — 7 Freescale Semiconductor ...

Page 47

... Note: Address lines A[0–17] hold their state after a read or write operation. AA[0–3] do not hold their state after a read or write operation. Figure 2-24. Bus Release Timings Case 1 (BRT Bit in Operating Mode Register Cleared) Freescale Semiconductor 212 213 215 Figure 2-23. ...

Page 48

... Note: Address lines A[0–17] hold their state after a read or write operation. AA[0–3] do not hold their state after a read or write operation. Figure 2-25. Bus Release Timings Case 2 (BRT Bit in Operating Mode Register Set) 2-28 214 213 221 223 DSP56303 Technical Data, Rev. 11 219 218 224 Freescale Semiconductor ...

Page 49

... DSP56300 components that are potential masters on the same bus asserted and is deasserted, another DSP56300 component may assume mastership at the same time. BB Therefore, some non-overlap period between one ensures that overlaps are avoided. Freescale Semiconductor Asynchronous Bus Timings 5 5 250 250+251 Asynchronous Bus Arbitration Timing ...

Page 50

... T + 9.9 19.9 — C 9.9 — — 19.3 0.0 — 4.6 — 3.3 — 0 — 4.6 — 3.3 — 5.3 15.3 — C 1.5 × 5.3 20.3 — C Freescale Semiconductor Unit ...

Page 51

... After the external host writes a new value to the ICR, the HI08 is ready for operation after three DSP clock cycles (3 × Tc). HACK H[0–7] HREQ Note: The IVR is read only by an MC680xx host processor in non-multiplexed mode. Figure 2-27. Freescale Semiconductor 1,2,12 Host Interface Timings ...

Page 52

... H[7–0] 340 341 HA[2–0] 336 337 330 HCS 317 HRD 328 332 327 326 H[7–0] 340 341 DSP56303 Technical Data, Rev. 11 333 337 318 319 329 338 333 318 319 329 338 Freescale Semiconductor ...

Page 53

... HTRQ (double host request) Figure 2-30. Write Timing Diagram, Non-Multiplexed Bus, Single Data Strobe HREQ (single host request) HTRQ (double host request) Figure 2-31. Write Timing Diagram, Non-Multiplexed Bus, Double Data Strobe Freescale Semiconductor HA[2–0] 336 337 331 HCS 336 ...

Page 54

... Read Timing Diagram, Multiplexed Bus, Single Data Strobe HA[10–8] 336 322 HAS 323 317 HRD 334 335 327 329 HAD[7–0] Address 326 340 341 DSP56303 Technical Data, Rev. 11 337 337 318 319 328 Data 338 337 318 319 328 Data 338 Freescale Semiconductor ...

Page 55

... HREQ (single host request) HTRQ (double host request) Figure 2-34. HA[10–8] HAD[7–0] HREQ (single host request) HTRQ (double host request) Figure 2-35. Write Timing Diagram, Multiplexed Bus, Double Data Strobe Freescale Semiconductor 336 322 HAS 323 336 HRW 320 HDS ...

Page 56

... C 15.0 — 25.0 50.0 — − 5.5 — 19 — 32.0 ns 18.0 — ns 0.0 — ns 9.0 — ns 640.0 — 310.0 — ns 310.0 — ns 290.0 — ns 290.0 — determined by the SCI clock ACC Freescale Semiconductor ...

Page 57

... SCLK (Output) 403 TXD RXD SCLK (Input) TXD RXD Figure 2-36. 1X SCLK (Output) TXD Figure 2-37. Freescale Semiconductor 400 402 401 404 Data Valid 405 406 Data Valid a) Internal Clock 400 402 401 407 408 Data Valid 409 410 Data Valid ...

Page 58

... Freescale Semiconductor Unit ...

Page 59

... If the DSP core writes to the transmit register during the last cycle before causing an underrun error, the delay (0.5 × expression is used to compute the number listed as the minimum or maximum value as appropriate. Freescale Semiconductor Table 2-18. ESSI Timings (Continued Symbol Expression 3 3 ...

Page 60

... In Normal mode, the output flag state is asserted for the entire frame period. 2-40 430 432 446 447 450 454 454 452 First 459 457 453 461 458 460 461 462 Figure 2-38. ESSI Transmitter Timing DSP56303 Technical Data, Rev. 11 451 455 Last 456 See Note Freescale Semiconductor ...

Page 61

... RXC (Input/ Output) FSR (Bit) Out FSR (Word) Out Data In FSR (Bit) In FSR (Word) In Flags In Freescale Semiconductor 430 431 432 433 434 437 440 439 Last Bit First Bit 443 441 443 442 444 445 Figure 2-39. ESSI Receiver Timing DSP56303 Technical Data, Rev. 11 ...

Page 62

... First Interrupt Instruction Execution Figure 2-41. Timer Interrupt Generation 484 Figure 2-42. External Pulse Generation DSP56303 Technical Data, Rev. 11 100 MHz 2 Min Max 22.0 — 22.0 — 9.0 10.0 + 1.0 103.5 — 5.5 — — 24.8 5.5 — — 24.8 485 Freescale Semiconductor Unit ...

Page 63

... J CLKOUT (Output) GPIO (Output) GPIO (Input) A[0–17] Fetch the instruction MOVE X0,X:(R0); X0 contains the new value of GPIO and R0 contains the address of the GPIO data register. Freescale Semiconductor Table 2-20. GPIO Timing Expression Minimum: 6.75 × 492 493 Valid 494 Figure 2-43 ...

Page 64

... DSP56303 Technical Data, Rev. 11 All frequencies Min Max 0.0 22.0 45.0 — 20.0 — 0.0 3.0 5.0 — 24.0 — 0.0 40.0 0.0 40.0 5.0 — 25.0 — 0.0 44.0 0.0 44.0 100.0 — 40.0 — 502 V M 503 Freescale Semiconductor Unit MHz ...

Page 65

... TDO (Output) TDO (Output) TDO (Output) Figure 2-46. TCK (Input) TRST (Input) Freescale Semiconductor 504 Input Data Valid 506 Output Data Valid 507 506 Output Data Valid Boundary Scan (JTAG) Timing Diagram 508 Input Data Valid 510 Output Data Valid ...

Page 66

... Expression Max 22.0 MHz 1.5 × T 5.5 × × –40°C to +100 ° pF 514 515 Figure 2-48. OnCE—Debug Request DSP56303 Technical Data, Rev. 11 Min Max Unit 0.0 22.0 MHz + 10.0 20.0 — 30.0 — 67 5.0 + 25.0 — 516 Freescale Semiconductor ...

Page 67

... This section includes diagrams of the DSP56303 package pin-outs and tables showing how the signals described in Chapter 1, are allocated for each package. The DSP56303 is available in two package types: • 144-pin Thin Quad Flat Pack (TQFP) • 196-pin Molded Array Process-Ball Grid Array (MAP-BGA) Freescale Semiconductor DSP56303 Technical Data, Rev 3-1 ...

Page 68

... DSP56303 Thin Quad Flat Pack (TQFP), Top View DSP56303 Technical Data, Rev AA0 AA1 RD WR GND C V CCC BCLK BCLK CLKOUT GND C V CCC V CCQ EXTAL GND Q XTAL CAS AA2 AA3 NC GND P1 GND P PCAP V CCP RESET HAD0 HAD1 HAD2 HAD3 GND H V CCH 37 HAD4 Freescale Semiconductor ...

Page 69

... Because of size constraints in this figure, only one name is shown for multiplexed pins. Refer to Table 3-1 and Table 3-2 for detailed information about pin functions and signal names. Figure 3-2. Freescale Semiconductor (Bottom View) DSP56303 Thin Quad Flat Pack (TQFP), Bottom View DSP56303 Technical Data, Rev ...

Page 70

... CCP 46 PCAP 47 GND P 48 GND P1 49 Not Connected (NC), reserved 50 AA3/RAS3 DSP56303 Technical Data, Rev. 11 Pin Signal Name No. 51 AA2/RAS2 52 CAS 53 XTAL 54 GND Q 55 EXTAL 56 V CCQ 57 V CCC 58 GND C 59 CLKOUT 60 BCLK 61 BCLK CCC 66 GND AA1/RAS1 70 AA0/RAS0 CCA 75 GND A Freescale Semiconductor ...

Page 71

... For example, Pin 34 is data line H7 in non-multiplexed bus mode, data/address line HAD7 in multiplexed bus mode, or GPIO line PB7 when the GPIO function is enabled for this pin. Freescale Semiconductor Pin Signal Name No ...

Page 72

... DE 5 EXTAL 55 GND 75 A GND 81 A GND 87 A GND 96 A GND 58 C GND 66 C GND 104 D GND 112 D GND 120 D GND 130 D GND 39 H GND 47 P GND 48 P1 GND 19 Q GND 54 Q GND 90 Q GND 127 Q GND 9 S GND Freescale Semiconductor ...

Page 73

... HA2 31 HA8 32 HA9 31 HACK/HACK 23 HAD0 43 HAD1 42 HAD2 41 HAD3 40 HAD4 37 HAD5 36 HAD6 35 HAD7 34 HAS/HAS 33 HCS/HCS 30 HDS/HDS 21 Freescale Semiconductor Pin Signal Name No. HRD/HRD 22 HREQ/HREQ 24 HRRQ/HRRQ 23 HRW 22 HTRQ/HTRQ 24 HWR/HWR 21 IRQA 137 IRQB 136 IRQC 135 IRQD 134 MODA 137 MODB 136 MODC 135 MODD ...

Page 74

... CCA V 95 CCA DSP56303 Technical Data, Rev. 11 Pin Signal Name No CCC V 65 CCC V 103 CCD V 111 CCD V 119 CCD V 129 CCD V 38 CCH V 45 CCP V 18 CCQ V 56 CCQ V 91 CCQ V 126 CCQ V 8 CCS V 25 CCS WR 67 XTAL 53 Freescale Semiconductor ...

Page 75

... T L Pin 1 144 ident Plating Base D metal 0. Section J1-J1 (rotated 90) 144 PL Figure 3-3. DSP56303 Mechanical Information, 144-pin TQFP Package Freescale Semiconductor 0. TIPS 109 108 View View AB 0.1 T θ 144X 2 Seating plane θ — 0.05 R2 θ R1 (K) ...

Page 76

... CCD GND GND CCD GND GND A17 A16 D0 GND GND V A14 A15 CCA GND GND A13 V A12 CCQ GND GND V A10 A11 CCA GND GND GND GND CCA GND GND CCA BCLK BCLK BR V AA0 A0 CCC TA BB AA1 BG NC Freescale Semiconductor ...

Page 77

... GND GND CCA GND CCA AA0 V BR CCC NC BG AA1 BB Figure 3-5. DSP56303 Molded Array Process-Ball Grid Array (MAP-BGA), Bottom View Freescale Semiconductor Bottom View D14 D16 D19 V D23 CCD D13 D15 D17 D20 D21 D12 V D18 V D22 CCD CCQ GND ...

Page 78

... GND D10 GND D11 GND D12 D1 D13 D2 D14 V CCD E1 STD0 or PC5 E2 V CCS E3 SRD0 or PC4 E4 GND E5 GND E6 GND E7 GND E8 GND E9 GND E10 GND E11 GND E12 A17 E13 A16 E14 D0 F1 RXD or PE0 F2 SC10 or PD0 F3 SC00 or PC0 F4 GND F5 GND Freescale Semiconductor ...

Page 79

... G9 GND G10 GND G11 GND G12 A13 G13 V CCQ G14 A12 CCQ L11 GND L12 V CCA L13 A3 L14 A4 Freescale Semiconductor Pin Signal Name No. H3 SCK0 or PC3 H4 GND H5 GND H6 GND H7 GND H8 GND H9 GND H10 GND H11 GND H12 V CCA H13 A10 H14 ...

Page 80

... H2, HAD2, or PB2 N5 RESET N6 GND P N7 AA3/RAS3 N8 CAS N9 V CCQ N10 BCLK N11 BR N12 V CCC N13 AA0/RAS0 N14 A0 DSP56303 Technical Data, Rev. 11 (Continued) Pin Signal Name No. P5 PCAP P6 GND P1 P7 AA2/RAS2 P8 XTAL P9 V CCC P10 TA P11 BB P12 AA1/RAS1 P13 BG P14 NC and P . Freescale Semiconductor ...

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... K13 A6 K14 A7 J13 A8 J12 A9 J14 AA0 N13 AA1 P12 AA2 P7 AA3 N7 BB P11 BCLK M10 BCLK N10 Freescale Semiconductor DSP56303 MAP-BGA Signal Identification by Name Pin Signal Name No. BG P13 BR N11 CAS N8 CLKOUT M9 D0 E14 D1 D12 D10 B11 D11 A11 D12 C10 ...

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... GND L6 GND L7 GND L8 GND L9 GND L10 GND L11 GND N6 P GND DSP56303 Technical Data, Rev. 11 Pin Signal Name No HA0 M3 HA1 M1 HA10 L1 HA2 M2 HA8 M1 HA9 M2 HACK/HACK J1 HAD0 M5 HAD1 P4 HAD2 N4 HAD3 P3 HAD4 N3 HAD5 P2 HAD6 N1 HAD7 N2 HAS/HAS M3 HCS/HCS L1 HDS/HDS J3 HRD/HRD J2 HREQ/HREQ K2 HRRQ/HRRQ J1 Freescale Semiconductor ...

Page 83

... IRQB A5 IRQC C5 IRQD B5 MODA C4 MODB A5 MODC C5 MODD A14 NC B14 P14 NMI D1 PB0 M5 PB1 P4 PB10 M2 PB11 J2 PB12 J3 PB13 L1 Freescale Semiconductor Pin Signal Name No. PB14 K2 PB15 J1 PB2 N4 PB3 P3 PB4 N3 PB5 P2 PB6 N1 PB7 N2 PB8 M3 PB9 M1 PC0 F3 PC1 D2 PC2 C1 PC3 H3 PC4 E3 PC5 E1 PCAP P5 PD0 F2 PD1 A2 ...

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... CCA V L12 CCA V N12 CCC V P9 CCC V A7 CCD V C9 CCD V C11 CCD V D14 CCD V M4 CCH DSP56303 Technical Data, Rev. 11 Pin Signal Name No CCP V C7 CCQ V G13 CCQ V H2 CCQ V N9 CCQ V E2 CCS V K1 CCS WR M11 XTAL P8 Freescale Semiconductor ...

Page 85

... To minimize temperature variation across the surface, the thermal resistance is measured from the junction to the outside surface of the package (case) closest to the chip mounting area when that surface has a proper heat sink. Freescale Semiconductor , in ° C can be obtained from this equation: J × ...

Page 86

... T )/ has been defined – CAUTION this high-impedance circuit. pin. power source to . GND and V CC DSP56303 Technical Data, Rev )/P . This value gives a better estimate pin on the DSP and from the V CC and V GND CC . GND , , IRQA IRQB IRQC Freescale Semiconductor pins , , IRQD ...

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... Set the EBD bit when you are not accessing external memory. 1. Minimize external memory accesses, and use internal memory accesses. 2. Minimize the number of pins that are switching. 3. Minimize the capacitive load on the pins. 4. Connect the unused inputs to pull-up or pull-down resistors. 5. Freescale Semiconductor and circuits. GND , , ). TMS DE , ...

Page 88

... F2 current at F1 high frequency (any specified operating frequency) low frequency (any specified operating frequency lower than F2) DSP56303 Technical Data, Rev. 11 and for a EXTAL CLKOUT and EXTAL CLKOUT . These CLKOUT . For small MF (MF < 10) CLKOUT Freescale Semiconductor ...

Page 89

... The phase and frequency jitter performance results are valid only if the input jitter is less than the prescribed values. Freescale Semiconductor is 0.5 percent. If the rate of change of the frequency of EXTAL DSP56303 Technical Data, Rev ...

Page 90

... Design Considerations 4-6 DSP56303 Technical Data, Rev. 11 Freescale Semiconductor ...

Page 91

... Load the program ; move #INT_PROG,r0 move #PROG_START,r1 do #(PROG_END-PROG_START),PLOAD_LOOP move p:(r1)+,x0 move x0,p:(r0)+ nop PLOAD_LOOP ; ; Load the X-data ; move #INT_XDAT,r0 move #XDAT_START,r1 do #(XDAT_END-XDAT_START),XLOAD_LOOP Freescale Semiconductor Typical Power Consumption ; XTAL disable ; PLL enable ; CLKOUT disable DSP56303 Technical Data, Rev A-1 ...

Page 92

... PROG_END nop nop XDAT_START ; org x:0 dc $262EB9 dc $86F2FE dc $E56A5F dc $616CAC dc $8FFD75 dc $9210A dc $A06D7B dc $CEA798 dc $8DFBF1 dc $A063D6 A-2 ; ebd y:(r4)+,y1 y:(r4)+,y0 y:(r4)+,y0 DSP56303 Technical Data, Rev. 11 Freescale Semiconductor ...

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... XDAT_END YDAT_START ; org y:0 dc $5B6DA dc $C3F70B Freescale Semiconductor DSP56303 Technical Data, Rev. 11 A-3 ...

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... A-4 DSP56303 Technical Data, Rev. 11 Freescale Semiconductor ...

Page 95

... HCR bits definition M_HRIE EQU $0 M_HTIE EQU $1 M_HCIE EQU $2 M_HF2 EQU $3 M_HF3 EQU $4 Freescale Semiconductor ; Host port GPIO data Register ; Host port GPIO direction Register ; Port C Control Register ; Port C Direction Register ; Port C GPIO Data Register ; Port D Control register ; Port D Direction Data Register ...

Page 96

... SCI Clock Control Register ; Word Select Mask (WDS0-WDS3) ; Word Select 0 ; Word Select 1 ; Word Select 2 ; SCI Shift Direction ; Send Break ; Wakeup Mode Select ; Receiver Wakeup Enable ; Wired-OR Mode Select ; SCI Receiver Enable ; SCI Transmitter Enable ; Idle Line Interrupt Enable DSP56303 Technical Data, Rev. 11 Freescale Semiconductor ...

Page 97

... M_CRB1 EQU $FFFFA6 M_CRA1 EQU $FFFFA5 M_TSMA1 EQU $FFFFA4 M_TSMB1 EQU $FFFFA3 M_RSMA1 EQU $FFFFA2 M_RSMB1 EQU $FFFFA1 Freescale Semiconductor ; SCI Receive Interrupt Enable ; SCI Transmit Interrupt Enable ; Timer Interrupt Enable ; Timer Interrupt Rate ; SCI Clock Polarity ; SCI Error Interrupt Enable (REIE) ...

Page 98

... Transmit Frame Sync Flag ; Receive Frame Sync Flag ; Transmitter Underrun Error FLag ; Receiver Overrun Error Flag ; Transmit Data Register Empty ; Receive Data Register Full ; SSI Transmit Slot Bits Mask A (TS0-TS15) ; SSI Transmit Slot Bits Mask B (TS16-TS31) DSP56303 Technical Data, Rev. 11 Freescale Semiconductor ...

Page 99

... M_D4L EQU $300000 M_D4L0 EQU 20 M_D4L1 EQU 21 M_D5L EQU $C00000 M_D5L0 EQU 22 M_D5L1 EQU 23 Freescale Semiconductor ; SSI Receive Slot Bits Mask A (RS0-RS15) ; SSI Receive Slot Bits Mask B (RS16-RS31) ; Interrupt Priority Register Core ; Interrupt Priority Register Peripheral ; IRQA Mode Mask ; IRQA Mode Interrupt Priority Level (low) ...

Page 100

... TIMER2 Compare Register ; TIMER2 Count Register ; TIMER Prescaler Load Register ; TIMER Prescalar Count Register ; Timer Enable ; Timer Overflow Interrupt Enable ; Timer Compare Interrupt Enable ; Timer Control Mask (TC0-TC3) ; Inverter Bit ; Timer Restart Mode ; Direction Bit DSP56303 Technical Data, Rev. 11 Freescale Semiconductor ...

Page 101

... M_DCO2 EQU $FFFFE5 M_DCR2 EQU $FFFFE4 ; Register Addresses Of DMA4 M_DSR3 EQU $FFFFE3 M_DDR3 EQU $FFFFE2 M_DCO3 EQU $FFFFE1 M_DCR3 EQU $FFFFE0 Freescale Semiconductor ; Data Input ; Data Output ; Prescaled Clock Enable ; Timer Overflow Flag ; Timer Compare Flag ; Prescaler Source Mask ; Timer Control 0 ...

Page 102

... DMA Channel Transfer Done Status 2 ; DMA Channel Transfer Done Status 3 ; DMA Channel Transfer Done Status 4 ; DMA Channel Transfer Done Status 5 ; DMA Active State ; DMA Active Channel Mask (DCH0-DCH2) ; DMA Active Channel 0 ; DMA Active Channel 1 ; DMA Active Channel 2 DSP56303 Technical Data, Rev. 11 Freescale Semiconductor ...

Page 103

... M_BRW EQU $C M_BPS EQU $300 M_BPLE EQU 11 M_BME EQU 12 M_BRE EQU 13 M_BSTR EQU 14 M_BRF EQU $7F8000 Freescale Semiconductor ; PLL Control Register ; Multiplication Factor Bits Mask (MF0-MF11) ; Division Factor Bits Mask (DF0-DF2) ; XTAL Range select bit ; XTAL Disable Bit ; STOP Processing State Bit ...

Page 104

... OMR ; Burst Enable ; TA Synchronize Select ; Bus Release Timing ; Address Tracing Enable bit in OMR. ; Stack Extension space select bit in OMR. ; Extensed stack UNderflow flag in OMR. ; Extended stack OVerflow flag in OMR. ; Extended WRaP flag in OMR. DSP56303 Technical Data, Rev. 11 Freescale Semiconductor ...

Page 105

... I_DMA3 EQU I_VEC+$1E I_DMA4 EQU I_VEC+$20 I_DMA5 EQU I_VEC+$22 ;------------------------------------------------------------------------ ; Timer Interrupts ;------------------------------------------------------------------------ I_TIM0C EQU I_VEC+$24 I_TIM0OF EQU I_VEC+$26 I_TIM1C EQU I_VEC+$28 Freescale Semiconductor ; Stack Extension Enable bit in OMR. ;leave user definition as is. ; Hardware RESET ; Stack Error ; Illegal Instruction ; Debug Request ; Trap ; Non Maskable Interrupt ...

Page 106

... ESSI1 Transmit last slot ; SCI Receive Data ; SCI Receive Data With Exception Status ; SCI Transmit Data ; SCI Idle Line ; SCI Timer ; Host Receive Data Full ; Host Transmit Data Empty ; Default Host Command ; last address of interrupt vector space DSP56303 Technical Data, Rev. 11 Freescale Semiconductor ...

Page 107

...

Page 108

... Freescale Semiconductor was negligent regarding the design or manufacture of the part. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 1996, 2005. Order Number DSP56303AG100 DSP56303PV100 DSP56303VL100 DSP56303VF100 ...

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