AD6623S/PCB Analog Devices Inc, AD6623S/PCB Datasheet - Page 18

• Manufacturer Part Number: AD6623S/PCB
• Description: BOARD EVAL SGNL PROCESSOR AD6623
• Manufacturer: Analog Devices Inc

Specifications of AD6623S/PCB

• Rohs Status: RoHS non-compliant
• Module/board Type: Evaluation Board
• For Use With/related Products: AD6623
• Lead Free Status / Rohs Status: Not Compliant

Signal
I and Q Inputs
Coefficients
Product
Sum
FIR Output
AD6623
The Scale and Ramp block adjusts the final magnitude of the
modulated RCF output. A synchronization pulse from the
SYNC0–3 pins or serial words can be used to command this
block to ramp down, pause, and ramp up to a new scale factor.
The shape of the ramp is stored in RAM, allowing complete
sample by sample control at the RCF interpolated rate. This is
particularly useful for time division multiplexed standards such
as GSM/EDGE. Modulator configurations can be updated
while the ramp is quiet, allowing for GSM and EDGE timeslots
to be multiplexed together without resetting or reconfiguring the
channel. Each of the RCF processing blocks is discussed in
greater detail in the following sections.
INTERPOLATING FIR FILTER
The Interpolating FIR Filter realizes a real, sum-of-products filter
on I and Q inputs using a single interleaved Multiply-Accumulator
(MAC) running at the CLK rate. The input signal is interpolated
by integer factors to produce arbitrary impulse responses up to
256 output samples long.
Each bus in the data path carries bipolar two’s complement values.
For the purpose of discussion, we will arbitrarily consider the radix
point positioned so that the input data ranges from –1 to just
below 1. In Figure 19, the data buses are marked x × y to denote
finite precision limitations. A bus marked x × y has x bits above
the radix and y bits below the radix, which implies a range from
–2
Table IV for each bus. The hexadecimal values are bit-exact and
each MSB has negative weight. Note that the Product bus range is
limited by result of the multiplication and the two most significant
bits are the same except in one case.
x–1
to 2
x–1
– 2
–y
in 2
x
1.15
1.15
2.18
4.18
1.17
–y
steps. The range limits are tabulated in
DATA FROM SERIAL PORT
y Notation
MODULATOR
PSK
Decimal
–1.00000
–1.00000
–0.99969
–7.00000
–1.00000
Table IV. FIR Filter Internal Precision
INTERPOLATING
INTERPOLATING
INTERPOLATING
MODULATOR
MODULATOR
Figure 18. RCF Block Diagram
FILTER
QPSK
MSK
FIR
Minimum
Hexadecimal (h)
+1.00000
+1.00000
+3.00020
+8.00000
+1.00000
–18–
The RCF realizes a FIR filter with optional interpolation. The
FIR filter can produce impulse responses up to 256 output
samples long. The FIR response may be interpolated up to a
factor of 256, although the best filter performance is usually
achieved when the RCF interpolation factor (L
to eight or below. The 256 × 16 coefficient memory (CMEM)
can be divided among an arbitrary number of filters, one of
which is selected by the Coefficient Offset Pointer (channel
address 0x0B). The polyphase implementation is an efficient
equivalent to an integer up-sampler followed FIR filter running
at the interpolated rate.
The AD6623 RCF realizes a sum-of-products filter using a
polyphase implementation. This mode is equivalent to an inter-
polator followed by a FIR filter running at the interpolated rate.
In the functional diagram below, the interpolating block in-
creases the rate by the RCF interpolation factor (L
L
block is a filter with a finite impulse response length (N
an impulse response of h[n], where n is an integer from 0 to N
The difference equation for Figure 20 is written below, where
h[n] is the RCF impulse response, b[n] is the interpolated input
sample sequence at point ‘b’ in the diagram above, and c[n] is
the output sample sequence at point ‘c’ in Figure 20.
RCF
–1 zero valued samples between every input sample. The next
EQUALIZER
Figure 19. Interpolating FIR Filter Block Diagram
ALLPASS
PHASE
256 16
DMEM
32 16
CMEM
COEF
INPUT
1.15
1.15
Decimal
0.999969
0.999969
1.000000
7.999996
0.999992
INPUT
1.15
DATA TO CIC FILTERS
PRODUCT
SCALE
ACCUMULATOR
RAMP
AND
Maximum
2.18
4.18
Hexadecimal (h)
0.FFFE
0.FFFE
1.00000
7.FFFFC
0.FFFF8
2
0
, 2
–1
RCF
, 2
RCF
–2
) is confined
, OR 2
) by inserting
OUTPUT
1.17
RCF
–3
REV. A
RCF
) and
–1.