AD6623S/PCB Analog Devices Inc, AD6623S/PCB Datasheet - Page 5

• Manufacturer Part Number: AD6623S/PCB
• Description: BOARD EVAL SGNL PROCESSOR AD6623
• Manufacturer: Analog Devices Inc

Specifications of AD6623S/PCB

• Rohs Status: RoHS non-compliant
• Module/board Type: Evaluation Board
• For Use With/related Products: AD6623
• Lead Free Status / Rohs Status: Not Compliant

GENERAL TIMING CHARACTERISTICS
Parameter (Conditions)
CLK Timing Requirements:
t
t
t
RESET Timing Requirement:
t
Input Data Timing Requirements:
t
t
Output Data Timing Characteristics:
t
t
SYNC Timing Requirements:
t
t
Master Mode Serial Port Timing Requirements (SCS = 0):
Switching Characteristics
t
t
t
t
t
t
t
t
t
t
t
t
Slave Mode Serial Port Timing Requirements (SCS = 1):
Switching Characteristics
t
t
t
t
t
t
t
t
t
t
t
NOTES
1
2
3
Specifications subject to change without notice.
REV. A
All Timing Specifications valid over VDD range of 2.375 V to 2.675 V and VDDIO range of 3.0 V to 3.6 V.
C
The timing parameters for SCLK, SDIN, SDFI, SDFO, and SYNC apply to all four channels (A, B, C, and D).
CLK
CLKL
CLKH
RESL
SI
HI
DO
DZO
SS
HS
DSCLK1
DSCLKH
DSCLKL
DSCLKLL
SSDI0
HSDI0
DSFO0A
SSFI0
HSFI0
SSDI0
HSDI0
DSFO0B
SCLK
SCLKL
SCLKH
SSDH
HSDH
DSFO1
SSFI1
HSFI1
SSDI1
HSDI1
DSFO1
LOAD
= 40 pF on all outputs (unless otherwise specified).
CLK Period
CLK Width Low
CLK Width High
RESET Width Low
INOUT[17:0], QIN to ↑CLK Setup Time
INOUT[17:0], QIN to ↑CLK Hold Time
↑CLK to OUT[17:0], INOUT[17:0],
QOUT Output Delay Time
OEN HIGH to OUT[17:0] Active
SYNC(0, 1, 2, 3) to ↑CLK Setup Time
SYNC(0, 1, 2, 3) to ↑CLK Hold Time
↑CLK to ↑SCLK Delay (divide by 1)
↑CLK to ↑SCLK Delay (for any other divisor)
↑CLK to ↓SCLK Delay
(divide by 2 or even number)
↓CLK to ↓SCLK Delay
(divide by 3 or odd number)
Channel is Self-Framing
SDIN to ↑SCLK Setup Time
SDIN to ↑SCLK Hold Time
↑SCLK to SDFO Delay
Channel is External-Framing
SDFI to ↑SCLK Setup Time
SDFI to ↑SCLK Hold Time
SDIN to ↑SCLK Setup Time
SDIN to ↑SCLK Hold Time
↑SCLK to SDFO Delay
SCLK Period
SCLK Low Time
SCLK High Time
Channel is Self-Framing
SDIN to ↑SCLK Setup Time
SDIN to ↑SCLK Hold Time
↑SCLK to SDFO Delay
Channel is External-Framing
SDFI to ↑ SCLK Setup Time
SDFI to ↑SCLK Hold Time
SDIN to ↑SCLK Setup Time
SDIN to ↑SCLK Hold Time
↓SCLK to SDFO Delay
3
3
1, 2
–5–
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Test
Level
I
IV
IV
I
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
Min
9.6
3
3
30.0
1
2
2
3
1
2
4
5
3.5
4
1.7
0
0.5
2
0
2
0
0.5
3.5
3.5
1
2.5
4
2
1
1
2.5
10
AD6623AS
Typ
0.5 × t
2
t
CLK
CLK
Max
6
7.5
10.5
13
9
10
3.5
3
10
AD6623
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns