AD6623S/PCB Analog Devices Inc, AD6623S/PCB Datasheet - Page 43

• Manufacturer Part Number: AD6623S/PCB
• Description: BOARD EVAL SGNL PROCESSOR AD6623
• Manufacturer: Analog Devices Inc

Specifications of AD6623S/PCB

• Rohs Status: RoHS non-compliant
• Module/board Type: Evaluation Board
• For Use With/related Products: AD6623
• Lead Free Status / Rohs Status: Not Compliant

from 0 Hz to 7.68 MHz (f
and CIC frequency response is shown in Figure 44, on the same
frequency scale. This figure demonstrates a good approximation
to a root-raised-cosine with a roll-off factor of 0.22, a passband
ripple of 0.1 dB, and a stopband ripple better than –70 dB until
the lobe of the first image which peaks at –60 dB about 7.68 MHz
from the carrier center. This lobe could be reduced by shifting
more of the interpolation towards the RCF, but that would
sacrifice near in performance. As shown, the first image can be
easily rejected by an analog filter further up the signal path.
Scaling must be considered as normal with an interpolation
factor of L, to guarantee no overflow in the RCF, CIC, or NCOs.
The output level at the summation port should be calculated
using an interpolation factor of L/N
Programming Multiple TSPs
Configuring the TSPs for de-interleaved operation is straight
forward. All the Channel Registers and the CMEM of each TSP
are programmed identically, except the Start Hold-Off Counters
and NCO Phase Offset.
In order to separate the input timing to each TSP, the Hold-Off
Counters must be used to start each TSP successively in response
to a common Start SYNC. The Start SYNC may originate from the
SYNC pin or the Microport. Each subsequent TSP must have a
Hold-Off Counter value L/N
TSPs are located on cascaded AD6623s, the Hold-Off Counters of
the upstream device should be incremented by an additional one.
In the UMTS example, L = 80 and N
quickly as possible to a Start SYNC, the Hold-Off Counter
values should be 1, 21, 41, and 61.
REV. A
3.84 MCPS
32
COMPLEX SIGNAL 32 BITS (16, I, 16 Q)
REAL OR IMAGINARY SIGNAL
RE-FORMATTER
IN
DATA
TSP
L
larger than its predecessor’s. If the
RCF
TSP
/N
TSP
TSP
.
MCPS
MCPS
MCPS
MCPS
0.96
0.96
32
32
32
0.96
32
0.96
). The composite RCF
= 4, so to respond as
Figure 40. Driving Multiple TSP Serial Ports
FILTER
FILTER
FILTER
FILTER
COEF
COEF
COEF
COEF
RAM
RAM
RAM
RAM
9.6MSPS
9.6MSPS
9.6MSPS
9.6MSPS
Q
Q
Q
Q
I
I
I
I
–43–
CIC
CIC
CIC
CIC
Driving Multiple TSP Serial Ports
When configured properly, the AD6623 will drive each SDFO
out of phase. Each new piece of data should be driven only into
the TSP that pulses its SDFO pin at that time.
In the UMTS example in Figure 41, L = 80 and N
serial port need only accept every fourth input sample. Each
serial port is shifting at peak capacity, so sample 1, 2, and 3 begin
shifting into Serial Ports B, C, and D before sample 0 is com-
pleted into Serial Port A.
76.8MSPS
76.8MSPS
76.8MSPS
76.8MSPS
Figure 42. Typical Impulse Response for WBCDMA
(Wide-Band Code Division Multiple Access)
SDFOA
SDFOB
SDFOC
SDFOD
1.0
0.5
0.0
NCO
NCO
NCO
NCO
0
0
5
Figure 41. UMTS Example
1
10
SUMMATION
BLOCK
2
15
COEFFICIENT
3
20
4
76.8 MSAMPLES/SEC
25
DAC
5
30
AD6623
TSP
6
35
= 4, so each
40
7