AD6623S/PCB Analog Devices Inc, AD6623S/PCB Datasheet - Page 34

• Manufacturer Part Number: AD6623S/PCB
• Description: BOARD EVAL SGNL PROCESSOR AD6623
• Manufacturer: Analog Devices Inc

Specifications of AD6623S/PCB

• Rohs Status: RoHS non-compliant
• Module/board Type: Evaluation Board
• For Use With/related Products: AD6623
• Lead Free Status / Rohs Status: Not Compliant

AD6623
The ramp unit when bypassed will have exactly 0 dB of gain and
can be ignored. When in use, the gain is dependant on what value
is stored in the last valid RMEM location. RMEM words are
14 bits [0–1), so when the value is positive full scale, the gain is
about –0.0005 dB; probably neglectable.
The RCF coefficients should be normalized to positive full scale.
This will yield the greatest dynamic range. The RCF is equipped
with an output scaler that ranges from 0 dB to –18.06 dB below
full scale in +6.02 dB steps. This attenuation can be used to par-
tially compensate for filter gain in the RCF. For example, if the
maximum gain of the RCF coefficients is +11.26 dB, the RCF
coarse scale should be set to 2 (+12.04 dB). This yields an RCF
output level and fine scale input level of –0.78 dB
The fine scale unit is left to turn a –0.78 dB level into a –5.59 dB
MICROPORT INTERFACE
The Microport interface is the communications port between the
AD6623 and the host controller. There are two modes of bus
operation: Intel nonmultiplexed mode (INM), and Motorola
nonmultiplexed mode (MNM) that is set by hard-wiring the
MODE pin to either ground or supply. The mode is selected based
on the use of the Microport control lines (DS or RD, DTACK or
RDY, RW, or WR) and the capabilities of the host processor. See
the timing diagrams for details on the operation of both modes.
The External Memory Map provides data and address registers
to read and write the extensive control registers in the Internal
Memory Map. The control registers access global chip functions
and multiple control functions for each independent channel.
Microport Control
All accesses to the internal registers and memory of the AD6623
are accomplished indirectly through the use of the microprocessor
port external registers shown in Table XXI. Accesses to the Exter-
nal Registers are accomplished through the 3 bit address bus
(A[2:0]) and the 8-bit data bus (D[7:0]) of the AD6623 (Microport).
External Address [3:0] provides access to data read from or written
to the internal memory (up to 32 bits). External Address [0] is the
least significant byte and External Address [3] is the most signifi-
cant byte. External Address [4] controls the Sleep Mode of each
11 26 12 04
– .
1 94 9 54 114 51 20 6 02
.
–
– .
Figure 38. AD6623 Stage-by-Stage Summary of Available Scaling and Power Ramping Functions
.
–
=
– .
0 78
.
+
SERIAL BASE-
BAND DATA IN
1 OF 4 CHANNELS
18-BIT
DIGITAL IF OUT
×
–12dB TO +6dB
HARD-WIRED
OUTPUT BIT
SCALING IS
AN OPTION
.
=
– .
5 59
COEFFICIENT
SCALING WILL
AFFECT NUMER-
ICAL MAGNITUDE
OF DATA
COEFFICIENT
SUMMATION
CHANNEL
FILTER
STAGE
RAM
0dB TO –18dB
ATTENUATION
RANGE WITH
2-BIT (6dB/STEP)
RESOLUTION
–6dB TO –24dB
ATTENUATION
RANGE WITH
2-BIT (6dB/STEP)
RESOLUTION
RCF COARSE
SCALING
SCALING
(23)
(24)
NCO
–34–
level. This requires a gain of –4.81 dB, which corresponds to a
14-bit [0–2] scale value of 1264h. All subsequent rescalings
during chip operation should be relative to this maximum.
Finally, as described in the RCF section, there may be a worst-case
peak of a phase that is larger than the channel center gain. In the
preceding example, if the worst case to channel center ratio is larger
than 4.59 dB (potentially overflowing the RCF), then the RCF_
Coarse_Scale should be reduced by one and the CIC_Scale should
be increased by one. In the preceding example, if the worst case to
channel center ratio is larger than 5.59 dB (potentially overflowing
the RCF and CIC), then the RCF_Coarse_Scale should be reduced
by one and the NCO_Output_Scale should be increased by one.
channel. External Address [5] controls the sync status of each
channel. External Address [7:6] determines the Internal Address
selected and whether this address is incremented after subsequent
reads and/or writes to the internal registers.
EXTERNAL MEMORY MAP
The External Memory Map is used to gain access to the Internal
Memory Map described below. External Address [7:6] sets the
Internal Address to which subsequent reads or writes will be per-
formed. The top two bits of External Address [7] allow the user
to set the address to auto increment after reads, writes, or both.
All internal data words have widths that are less than or equal to
32 bits. Accesses to External Address [0] also triggers access to
the AD6623’s internal memory map. Thus during writes to the
Internal Registers, External Address [0] must be written last to
insure all data is transferred. Reads are the opposite in that External
Address [0] must be the first data register read (after setting the
appropriate internal address) to initiate an internal access.
External Address [5:4] reads and writes are transferred immediately
to Internal Control Registers. External Address [4] is the sleep register.
The sleep bits can be set collectively by the address. The sleep bits
can be cleared by operation of start syncs as shown in Table XXI.
– .
floor
INTERPOLATION
MULTIPLIER
RANGE IS FROM
0 TO 2 WITH 16-BIT
RESOLUTION
5 59 0 78
MULTIPLIER
RCF FINE
SCALING
FILTERS



CIC
10
– .
– .
4 81
20
=
×
– .
2
RAMP MULTIPLIER
RANGE 0 TO 1 WITH
14-BIT RESOLUTION
AND UP TO 128
RAMP/DOWN STEPS
13
4 81
0dB TO –186dB,
6dB STEPS
WITH 5-BIT
RESOLUTION
RCF POWER
MULTIPLIER

 =

RAMPING
SCALING
CIC
1264
h
REV. A
(25)
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