XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet
XRT94L33IB-L
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XRT94L33IB-L Summary of contents
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET N0VEMBER 2006 GENERAL DESCRIPTION The XRT94L33 is a highly integrated SONET/SDH terminator designed for mapping/de-mapping functions from either the STS-3 or STM-1 data stream. The XRT94L33 interfaces directly to the optical ...
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... Intf SONET/SDH POH Telecom Bus To DS3/E3 Interface STS-1 Telecom Bus/ T3/E3/HDLC Intf ORDERING INFORMATION P N ART UMBER XRT94L33IB SONET/SDH POH SDH MUX DS3/E3 Jitter Attenuator Mapper DS3/E3 & Framer Clock Smoothing Pointer Justify HDLC Controller STS-1 Tx/Rx TOH & POH STS-1 Channel 0 ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET PIN DESCRIPTION of the XRT94L33 (Rev I/O IN IGNAL AME Y22 PCLK I AD25 PTYPE_0 I AD23 PTYPE_1 AC21 PTYPE_2 S D IGNAL T YPE M ...
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XRT94L33 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET Rev.1.2. I/O IN IGNAL AME AD27 PADDR_0 I AB25 PADDR_1 W23 PADDR_2 Y24 PADDR_3 AD26 PADDR_4 AC25 PADDR_5 AA24 PADDR_6 Y23 PADDR_7 AE24 PADDR_8 AB20 PADDR_9 AD22 ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET I/O IN IGNAL AME AF22 PWR_L IGNAL T YPE TTL Write Strobe/Read-Write Operation Identifier: The exact function of this input pin depends upon ...
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XRT94L33 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET Rev.1.2. I/O IN IGNAL AME AC18 PRD_L/ I DS*/ WE* S IGNAL T YPE TTL READ Strobe /Data Strobe: The exact function of this input pin depends ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET I/O IN IGNAL AME AG23 ALE/ I AS_L AE19 PCS_L I S IGNAL T YPE TTL Address Latch Enable/Address Strobe: The exact function of this input pin ...
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XRT94L33 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET Rev.1.2. I/O IN IGNAL AME AD18 PRDY_L/ O DTACK* RDY S IGNAL T YPE CMOS READY or DTACK Output: The exact function of this input pin depends ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET I/O IN IGNAL AME AF21 PDBEN_L I AF20 PBLAST_L I AG22 PINT_L O AB24 RESET_L I AE18 DIRECT_ADD_SEL I T3 RXLDAT_P I S IGNAL T YPE TTL ...
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XRT94L33 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET Rev.1.2. I/O IN IGNAL AME T2 RXLDAT_N I U2 RXLDAT_R_P I U1 RXLDAT_R_N I AE27 RXCLK_19MHZ O P3 REFCLK_P I S IGNAL T YPE LVPECL Receive STS-3/STM-1 ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET I/O IN IGNAL AME P2 REFCLK_N I P5 TXLDATO_P O P6 TXLDATO_N O M4 TXLDATO_R_P O S IGNAL T YPE LVPECL Transmit Reference Clock – Negative Polarity ...
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XRT94L33 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET Rev.1.2. I/O IN IGNAL AME M3 TXLDATO_R_N O N6 TXLCLKO_P O N5 TXLCLKO_N O M1 TXLCLKO_R_P O S IGNAL T YPE LVPECL Transmit STS-3/STM-1 Data Output - ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET I/O IN IGNAL AME M2 TXLCLKO_R_N O P1 REFTTL I S IGNAL T YPE LVPECL Transmit STS-3/STM-1 Clock – Negative Polarity PECL Output – Redundant Port: This ...
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XRT94L33 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET Rev.1.2. I/O IN IGNAL AME AG3 LOSTTL I AG25 LOSTTL_R I L4 LOSPECL_P I L3 LOSPECL_R I V1 LOCKDET O S IGNAL T YPE TTL Loss of ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET STS-3/STM TXA_CLK/ O TxAPSCLK I/O F2 TXA_C1J1 – ELECOM US NTERFACE RANSMIT CMOS Transmit STS-3/STM-1 Telecom Bus Interface - Clock Output Signal: This output ...
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XRT94L33 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET Rev.1.2.0. E2 TXA_ALARM/ O TxAPSPAR I/O H3 TXA_DP O CMOS Transmit STS-3/STM-1 Telecom Bus Interface – Alarm TTL/ Indicator Output signal: CMOS This output pin pulses “high”, coincident to the instant ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET G4 TxSBFP I K5 TxA_PL/ O TxAPSReq I/O TTL Transmit STS-3/STM-1 Frame Alignment Sync Input: The Transmit STS-3 TOH Processor Block can be configured to initiate its generation of a new ...
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XRT94L33 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET Rev.1.2.0. J4 TxA_D0/ O TxAPSDat0 O I/O G3 TxA_D1/ TxAPSDat1 D1 TxA_D2/ TxAPSDat2 F3 TxA_D3/ TxAPSDat3 J5 TxA_D4/ TxAPSDat4 H4 TxA_D5/ TxAPSDat5 D2 TxA_D6/ TxAPSDat6 E3 TxA_D7/ TxAPSDat7 STS-3/STM ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET AA3 RxD_PL I AD1 RxD_C1J1/ I RxAPSVal I/O TTL Receive STS-3/STM-1 Telecom Bus Interface – Payload Data Indicator Output Signal: This input pin indicates whether or not the Receive STS-3/STM-1 Telecom ...
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XRT94L33 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET Rev.1.2.0. AB3 RxD_DP I W1 RxD_ALARM/ I RxAPSPAR I/O TTL Receive STS-3/STM-1 Telecom Bus Interface – Parity Input pin: This input pin can be configured to function as one of the ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET Y2 RxD_D0/ I RxHRDat0/ I RxAPSDat0 I/O AD2 RxD_D1 RxHRDat1/ RxAPSDat1 AC3 RxD_D2 RxHRDat2/ RxAPSDat2 AA4 RxD_D3 RxHRDat3/ RxAPSDat3 AB4 RxD_D4 RxHRDat4/ RxAPSDat4 Y1 RxD_D5 RxHRDat5/ RxAPSDat5 AD3 RxD_D6 RxHRDat6/ RxAPSDat6 ...
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XRT94L33 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET Rev.1.2.0. SONET/SDH O H6 TxTOHClk O G5 TxTOHEnable O I – VERHEAD NTERFACE RANSMIT IRECTION CMOS Transmit TOH Input Port – Clock Output: This output pin, along “TxTOHFrame” output ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET F8 TxTOH I E8 TxTOHFrame O TTL Transmit TOH Input Port – Input pin: This input pin, along with the “TxTOHIns” input pin, the “TxTOHEnable” and “TxTOHFrame” and “TxTOHClk” output pins ...
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XRT94L33 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET Rev.1.2.0. D6 TxTOHIns I TTL Transmit TOH Input Port – Insert Enable Input pin: This input pin, along with the “TxTOH” input pin, and the “TxTOHEnable”, “TxTOHFrame” and “TxTOHClk” output pins ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET B4 TxLDCCEnable O D7 TxSDCCEnable O CMOS Transmit – Line DCC Input Port – Enable Output pin: This output pin, along with the “TxTOHClk” output pin and the “TxLDCC” input pin ...
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XRT94L33 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET Rev.1.2.0. C5 TxSDCC I D8 TxLDCC I TTL Transmit - Section DCC Input Port – Input pin: This input pin, along with the “TxSDCCEnable” and the “TxTOHClk” output pins permit the ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET E9 TxE1F1E2Enable O C6 TxE1F1E2Frame O A4 TxE1F1E2 I CMOS Transmit E1-F1-E2 Byte Input Port – Enable (or Ready) Indicator Output pin: This output pin, along with the “TxTOHClk” output pin ...
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XRT94L33 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET Rev.1.2.0. C7 TXPOH I D9 TXPOHCLK O TTL Transmit Path Overhead Input Port – Input pin. This pin is used for the Transmit AU-4/VC-4 Mapper POH Processor Block when TUG-3 mapping ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET B5 TXPOHFRAME O C8 TXPOHINS I B6 TXPOHENABLE O TTL Transmit Path Overhead Input Port – Frame Output pin: This pin is used for the Transmit AU-4/VC-4 Mapper POH Processor Block ...
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XRT94L33 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET Rev.1.2.0. E10 TxPOH_0 I B8 TxPOH_1 D11 TxPOH_2 A5 TxPOHClk_0 O A6 TxPOHClk_1 A7 TxPOHClk_2 TTL Transmit Path Overhead Input Port – Input pin. These input pins permit the user to ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET C9 TxPOHFrame_0 O C10 TxPOHFrame_1 A8 TxPOHFrame_2 D10 TxPOHIns_0 I E11 TxPOHIns_1 C11 TxPOHIns_2 B7 TxPOHEnable_0 O B9 TxPOHEnable_1 B10 TxPOHEnable_2 CMOS Transmit Path Overhead Input Port – Frame Output pin: ...
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XRT94L33 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET Rev.1.2.0. C12 TXDS3CLK_0 I TXE3CLK_0 B20 TXDS3CLK_1 I TXE3CLK_1 TTL Transmit DS3/E3 Reference Clock Input – Channel 0 (Not used for Mapper Applications): The exact manner in which the user should ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET AF17 TXDS3CLK_2 I TXE3CLK_2 B11 TxOHClk_0 O A22 TxOHClk_1 AD16 TxOHClk_2 TTL Transmit DS3/E3 Reference Clock Input – Channel 2 (Not used for Mapper Applications): The exact manner in which the ...
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XRT94L33 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET Rev.1.2.0. D12 TxOHENABLE_0 O C18 TxOHENABLE_1 AC16 TxOHENABLE_2 CMOS Transmit Overhead Enable Output indicator This output pin functions as the “Transmit Overhead Enable” output indicator for the transmit system side interface ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET E12 TxOH_0 I E17 TxOH_1 AB16 TxOH_2 TTL Transmit Overhead Data Input: This input pin functions as the “Transmit Overhead Data” output indicator for the transmit system side interface when the ...
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XRT94L33 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET Rev.1.2.0. E12 TxOH_0 I E17 TxOH_1 AB16 TxOH_2 TTL Continued If the user is only inserting POH data via these input pins: In this mode, the external circuitry (which is being ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET E12 TxOH_0 I E17 TxOH_1 AB16 TxOH_2 TTL Continued If the user is inserting both POH and TOH data via these input pins: In this mode, the external circuitry (which is ...
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XRT94L33 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET Rev.1.2.0. F12 TxOHINS_0 I B19 TxOHINS_1 AG19 TxOHINS_2 TTL Transmit Overhead Data Insert Input: This input pin functions as the “Transmit Overhead Data Insert” input indicator for the transmit system side ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET A9 TxOHFRAME_0 O D17 TxOHFRAME_1 AF18 TxOHFRAME_2 CMOS Transmit Overhead Framing Pulse: This input pin functions as the “Transmit Overhead Framing” Pulse for the transmit system side interface when the XRT94L33 ...
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XRT94L33 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET Rev.1.2.0. AF19 STUFFCNTL_0/ I/O TXHDLC_CLK_0/ AG21 STUFFCNTL_1/ TXHDLC_CLK_1/ AE17 STUFFCNTL_2/ TXHDLC_CLK_2/ TTL/CMOS Transmit PLCP Processor Block – Nibble Trailer Stuff Control Input pin/Transmit High-Speed HDLC Controller Input Interface – Clock Output ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET AC17 EIGHTKHZSYNC_0/ I/O RXHDLC_CLK_0/ AD17 EIGHTKHZSYNC_1/ RXHDLC_CLK_1/ AG20 EIGHTKHZSYNC_2/ RXHDLC_CLK_2/ D27 TXPERR I G25 TxPEOP I F25 TxMOD_0 I J24 TxUPRTY/ I TxPPRTY TTL/CMOS Transmit PLCP Processor Alignment Input/Receive High-Speed HDLC ...
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XRT94L33 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET Rev.1.2.0. H27 TxUDATA_0/ I TxPDATA_0 G27 TxUDATA_1/ TxPDATA_1 L24 TxUDATA_2/ TxPDATA_2 J26 TxUDATA_3/ TxPDATA_3 L23 TxUDATA_4/ TxPDATA_4 K25 TxUDATA_5/ TxPDATA_5 F27 TxUDATA_6/ TxPDATA_6 H26 TxUDATA_7/ TxPDATA_7 G26 TxUDATA_8/ TxPDATA_8 K24 TxUDATA_9/ ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET STS – ELECOM US NTERFACE RANSMIT IRECTION 43 XRT94L33 Rev.1.2.0. ...
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XRT94L33 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET Rev.1.2.0. C14 STS1TXA_CK_0 I TXSENDFCS_0 I TXGFCCLK_0 O TTL STS-1 Transmit Telecom Bus Clock Input pin/Transmit HDLC Control Block Send FCS Command Input pin – TTL Channel 0: CMOS The exact ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET E19 STS1TXA_CK_1 I TXSENDFCS_1 I TXGFCCLK_1 O TTL STS-1 Transmit Telecom Bus Clock Input pin/Transmit HDLC Control Block Send FCS Command Input pin – TTL Channel 1: CMOS The exact function ...
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XRT94L33 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET Rev.1.2.0. AC14 STS1TXA_CK_2 IO TXSENDFCS_2 TXGFCCLK_2 TTL STS-1 Transmit Telecom Bus Clock Input pin/Transmit HDLC Control Block Send FCS Command Input pin – CMOS Channel 2: CMOS The exact function of ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET E14 STS1TXA_PL_0 I TXSENDMSG_0 TTL STS-1 Transmit Telecom Bus – Payload Indicator Signal input/Transmit HDLC Controller block Send Message Command Input pin – Channel 0: The exact function of this input ...
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XRT94L33 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET Rev.1.2.0. C22 STS1TXA_PL_1 I TXSENDMSG_1: TTL STS-1 Transmit Telecom Bus – Payload Indicator Signal input/Transmit HDLC Controller block Send Message Command Input pin – Channel 1: The exact function of this ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET AD14 STS1TXA_PL_2 I TXSENDMSG_2: TTL STS-1 Transmit Telecom Bus – Payload Indicator Signal input/Transmit HDLC Controller block Send Message Command Input pin – Channel 2: The exact function of this input ...
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XRT94L33 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET Rev.1.2.0. D14 STS1TXA_C1J1_0 I RXDS3LINECLK_0 TTL STS-1 Transmit Telecom Bus C1/J1 Byte Phase Indicator Input Signal/Receive DS3/E3/STS-1 Clock Input from LIU (Channel 0): The exact function of this pin depends upon ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET A24 STS1TXA_C1J1_1 I RXDS3LINECLK_1/ RxSTS1LineClk_1 TTL Transmit STS-1 Telecom Bus Interface - C1/J1 Byte Phase Indicator Input Signal – Channel 1/Receive DS3/E3/STS-1 Clock Input from LIU – Channel 1: The exact ...
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XRT94L33 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET Rev.1.2.0. AF14 STS1TXA_C1J1_2 I RXDS3LINECLK_2 TTL STS-1 Transmit Telecom Bus C1/J1 Byte Phase Indicator Input Signal/Receive DS3/E3/STS-1 Clock Input from LIU (Channel 2): The exact function of this pin depends upon ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET B14 STS1TXA_DP_0 I RXDS3POS_0 TTL STS-1 Transmit Telecom Bus – Parity Input pin/Receive DS3/E3/STS-1 Positive-Polarity Data Input from LIU – Channel 0: The exact function of this pin depends upon whether ...
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XRT94L33 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET Rev.1.2.0. C21 STS1TXA_DP_1 I RXDS3POS_1 TTL STS-1 Transmit Telecom Bus – Parity Input pin/Receive DS3/E3/STS-1 Positive-Polarity Data Input from LIU Channel 1: The exact function of this input pin depends upon ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET AG15 STS1TXA_DP_2 I RXDS3POS_2 TTL STS-1 Transmit Telecom Bus – Parity Input pin/Receive DS3/E3/STS-1 Positive-Polarity Data Input from LIU – Channel 2; The exact function of this pin depends upon whether ...
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XRT94L33 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET Rev.1.2.0. A13 STS1TXA_ALARM_0 I RXDS3NEG_0 RxLCV_0 TTL Transmit STS-1 Telecom Input/Receive DS3/E3 Negative-Polarity Data Input from LIU/Receive DS3/E3 Line Code Violation Input from LIU – Channel 0; The exact function of ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET D19 STS1TXA_ALARM_1 I RXDS3NEG_1 RxLCV_1 TTL Transmit STS-1 Telecom Input/Receive DS3/E3 Negative-Polarity Data Input from LIU/Receive DS3/E3 Line Code Violation Input from LIU – Channel 1: The exact function of this ...
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XRT94L33 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET Rev.1.2.0. AF15 STS1TXA_ALARM_2 I RXDS3NEG_2 RxLCV_2 TTL Transmit STS-1 Telecom Input/Receive DS3/E3 Negative-Polarity Data Input from LIU/Receive DS3/E3 Line Code Violation Input from LIU – Channel 2: The exact function of ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET B13 STS1TXA_D0_0 I/O TXHDLCDAT_0_0 TXGFCMSB_0 C13 STS1TXA_D1_0 I TXHDLCDAT_1_0 TXGFC_0 TTL/CMOS Transmit STS-1 Telecom Bus – Channel 0 – Input Data Bus pin number 0 The exact function of this pin ...
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XRT94L33 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET Rev.1.2.0. D13 STS1TXA_D2_0 I TXHDLCDAT_2_0 TXCELLTXED_0 E13 STS1TXA_D3_0 I/O TXHDLCDAT_3_0 SSI_CLK A12 STS1TXA_D4_0 IO TXHDLCDAT_4_0 TXDS3OHIND_0 TTL/CMOS Transmit STS-1 Telecom Bus – Channel 0 – Input Data Bus pin number 2: ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET A11 STS1TXA_D5_0 I/O TXHDLCDAT_5_0 TXDS3FP_0 B12 STS1TXA_D6_0 I TXHDLCDAT_6_0 TXDS3DATA_0 TXSBDATA_6_0 TTL/CMOS Transmit STS-1 Telecom Bus – Channel 0 – Input Data Bus pin number 5: The exact function of this ...
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XRT94L33 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET Rev.1.2.0. A10 STS1TXA_D7_0 I TXHDLCDAT_7_0 TXAISEN_0 TXSBDATA_7_0 B23 STS1TXA_D0_1 I/O TXHDLCDAT_0_1 TXGFCMSB_1 TTL Transmit STS-1 Telecom Bus – Channel 0 – Input Data Bus pin number 7: The exact function of ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET C20 STS1TXA_D1_1 I TXHDLCDAT_1_1 TXGFC_1 B22 STS1TXA_D2_1 I/O TXHDLCDAT_2_1 TXCELLTXED_1 E18 STS1TXA_D3_1 I/O TXHDLCDAT_3_1 SSI_POS TTL Transmit STS-1 Telecom Bus – Channel 1 – Input Data Bus pin number 1: The ...
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XRT94L33 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET Rev.1.2.0. A23 STS1TXA_D4_1 I/O TXHDLCDAT_4_1 TXDS3OHIND_1 TTL/CMOS Transmit STS-1 Telecom Bus – Channel 1 – Input Data Bus pin number 4: The exact function of this pin depends upon whether the ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET C19 STS1TXA_D5_1 I/O TXHDLCDAT_5_1 TXDS3FP_1 D18 STS1TXA_D6_1 I TXHDLCDAT_6_1 TXDS3DATA_1 TTL/CMOS Transmit STS-1 Telecom Bus – Channel 1 – Input Data Bus pin number 5: The exact function of this pin ...
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XRT94L33 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET Rev.1.2.0. B21 STS1TXA_D7_1 I TXHDLCDAT_7_1 TXAISEN_1 AE15 STS1TXA_D0_2 I/O TXHDLCDAT_0_2 TXGFCMSB_2 TTL Transmit STS-1 Telecom Bus – Channel 1 – Input Data Bus pin number 7: The exact function of this ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET AD15 STS1TXA_D1_2 I TXHDLCDAT_1_2 TXGFC_2 AC15 STS1TXA_D2_2 I/O TXHDLCDAT_2_2 TXCELLTXED_2 AG16 STS1TXA_D3_2 I/O TXHDLCDAT_3_2 SSI_NEG TTL Transmit STS-1 Telecom Bus – Channel 2 – Input Data Bus pin number 1: The ...
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XRT94L33 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET Rev.1.2.0. AG17 STS1TXA_D4_2 I/O TXHDLCDAT_4_2 TXDS3OHIND_2 AF16 STS1TXA_D5_2 I/O TXHDLCDAT_5_2 TXDS3FP_2 AG18 STS1TXA_D6_2 I TXHDLCDAT_6_2 TXDS3DATA_2 TTL/CMOS Transmit STS-1 Telecom Bus – Channel 2 – Input Data Bus pin number 4: ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET AE16 STS1TXA_D7_2 I TXHDLCDAT_7_2 TXAISEN_2 TTL Transmit STS-1 Telecom Bus – Channel 2 – Input Data Bus pin number 7: The exact function of this pin depends upon whether the STS- ...
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XRT94L33 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET Rev.1.2.0. B15 RxOH_0 O C23 RxOH_1 AG13 RxOH_2 CMOS Receive Overhead Data Output Interface – output This output pin functions as the “Receive Overhead Data” output for the receive system side ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET C15 RxOHENABLE_0 O D21 RxOHENABLE_1 AF13 RxOHENABLE_2 D15 RxOHCLK_0 O E20 RxOHCLK_1 AE13 RxOHCLK_2 CMOS Receive Overhead Data Output Interface – Enable Output This output pin functions as the “Receive Overhead ...
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XRT94L33 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET Rev.1.2.0. E15 RxOHFRAME_0 O D22 RxOHFRAME_1 AD13 RxOHFRAME_2 Y26 RxPERR O AB27 RxPEOP O AA26 RxPDVAL O V24 RxMOD_0 O V25 RxUPRTY/ O RxPPRTY CMOS Receive Overhead Data Interface – Framing ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET U23 RxUDATA_0/ O RxPDATA_0 W26 RxUDATA_1/ RxPDATA_1 U24 RxUDATA_2/ RxPDATA_2 AA27 RxUDATA_3/ RxPDATA_3 Y27 RxUDATA_4/ RxPDATA_4 U25 RxUDATA_5/ RxPDATA_5 V26 RxUDATA_6/ RxPDATA_6 W27 RxUDATA_7/ RxPDATA_7 T23 RxUDATA_8/ RxPDATA_8 T24 RxUDATA_9/ RxPDATA_9 ...
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XRT94L33 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET Rev.1.2.0. N27 RXUCLK/ I RXPCLK A16 EXTLOS_0 I J23 EXTLOS_1 AC13 EXTLOS_2 A14 RxOOF_0 O D20 RxOOF_1 AE14 RxOOF_2 A15 RxLOS_0 O B24 RxLOS_1 AG14 RxLOS_2 TTL For mapper applications, Please ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET STS-1 T A21 STS1RXD_CK_0 O RXVALIDFCS_0 RXGFCCLK_0 B I – ELECOM US NTERFACE ECEIVE IRECTION CMOS Receive STS-1/STS-3 Telecom Bus Clock Output – Channel 0; The exact function of ...
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XRT94L33 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET Rev.1.2.0. H24 STS1RXD_CK_1 O RXVALIDFCS_1 RXGFCCLK_1 TxP_STPA AG8 STS1RXD_CK_2 O RXVALIDFCS_2 RXGFCCLK_2 CMOS Receive STS-1 Telecom Bus Clock Output – Channel 1; The exact function of this input pin depends upon ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET A20 STS1RXD_PL_0 O RXIDLE_0 RXLCD_0 D26 STS1RXD_PL_1 O RXIDLE_1 RXLCD_1 CMOS STS-1 Receive (Drop) Telecom Bus – Payload Indicator Output Signal – Channel 0: The exact function of this output pin ...
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XRT94L33 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET Rev.1.2.0. AE11 STS1RXD_PL_2 O RXIDLE_2 RXLCD_2 CMOS STS-1 Receive (Drop) Telecom Bus – Payload Indicator Output Signal – Channel 2: The exact function of this output pin depends upon whether the ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET C17 STS1RXD_C1J1_0 O TXDS3LINECLK_0 CMOS STS-1 Receive Telecom Bus - C1/J1 Byte Phase Indicator Output Signal – Channel 0: The exact function of this output pin depends upon whether the STS-1 ...
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XRT94L33 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET Rev.1.2.0. E25 STS1RXD_C1J1_1 O TXDS3LINECLK_1 CMOS STS-1 Receive Telecom Bus - C1/J1 Byte Phase Indicator Output Signal – Channel 1: The exact function of this output pin depends upon whether the ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET AF10 STS1RXD_C1J1_2 O TXDS3LINECLK_2 CMOS STS-1 Receive Telecom Bus - C1/J1 Byte Phase Indicator Output Signal – Channel 2: The exact function of this output pin depends upon whether the STS-1 ...
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XRT94L33 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET Rev.1.2.0. B18 STS1RXD_DP_0 O TXDS3POS_0 G24 STS1RXD_DP_1 O TXDS3POS_1 CMOS STS-1 Receive (Drop) Telecom Bus – Parity Output pin – Channel 0: The exact function of this output pin depends upon ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET AG9 STS1RXD_DP_2 O TXDS3POS_2 A19 STS1RXD_ALARM_0 O TXDS3NEG_0/ CMOS STS-1 Receive (Drop) Telecom Bus – Parity Output pin – Channel 2: The exact function of this output pin depends upon whether ...
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XRT94L33 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET Rev.1.2.0. H23 STS1RXD_ALARM_1 O TXDS3NEG_1/ AB12 STS1RXD_ALARM_2 O TXDS3NEG_2/ F16 STS1RXD_D0_0 O RXHDLCDAT_0_0 RXGFCMSB_0 CMOS STS-1 Receive (Drop) Telecom Bus – Alarm Indicator Output signal – Channel 1: The exact function ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET E16 STS1RXD_D1_0 O RXHDLCDAT_1_0 RXGFC_0 D16 STS1RXD_D2_0 O RXHDLCDAT_2_0 RXCELLRXED_0 CMOS Receive STS-1 Telecom Bus – Channel 0 – Output Data Bus pin number 1: The exact function of this output ...
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XRT94L33 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET Rev.1.2.0. B17 STS1RXD_D3_0 O RXHDLCDAT_3_0 O SSE_CLK IO O C16 STS1RXD_D4_0 O RXHDLCDAT_4_0 RXOHIND_0 A18 STS1RXD_D5_0 O RXHDLCDAT_5_0 RXDS3FP_0 CMOS Receive STS-1 Telecom Bus – Channel 0 – Output Data Bus ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET B16 STS1RXD_D6_0 O RXHDLCDAT_6_0 RXDS3DATA_0 A17 STS1RXD_D7_0 O RXHDLCDAT_7_0 RXDS3CLK_0 CMOS Receive STS-1 Telecom Bus – Channel 0 – Output Data Bus pin number 6: The exact function of this output ...
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XRT94L33 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET Rev.1.2.0. F24 STS1RXD_D0_1 O RXHDLCDAT_0_1 RXGFCMSB_1 H22 STS1RXD_D1_1 O RXHDLCDAT_1_1 RXGFC_1 CMOS Receive STS-1 Telecom Bus – Channel 1 – Output Data Bus pin number 0: The exact function of this ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET D25 STS1RXD_D2_1 O RXHDLCDAT_2_1 RXCELLRXED_1 G23 STS1RXD_D3_1 O RXHDLCDAT_3_1 O SSE_POS IO O CMOS Receive STS-1 Telecom Bus – Channel 1 – Output Data Bus pin number 2: The exact function ...
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XRT94L33 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET Rev.1.2.0. D23 STS1RXD_D4_1 O RXHDLCDAT_4_1 RXOHIND_1 E21 STS1RXD_D5_1 O RXHDLCDAT_5_1 RXDS3FP_1 C24 STS1RXD_D6_1 O RXHDLCDAT_6_1 RXDS3DATA_1 CMOS Receive STS-1 Telecom Bus – Channel 1 – Output Data Bus pin number 4: ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET F20 STS1RXD_D7_1 O RXHDLCDAT_7_1 RXDS3CLK_1 AC12 STS1RXD_D0_2 O RXHDLCDAT_0_2 RXGFCMSB_2 CMOS Receive STS-1 Telecom Bus – Channel 1 – Output Data Bus pin number 7: The exact function of this output ...
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XRT94L33 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET Rev.1.2.0. AD12 STS1RXD_D1_2 O RXHDLCDAT_1_2 RXGFC_2 AF11 STS1RXD_D2_2 O RXHDLCDAT_2_2 RXCELLRXED_2 CMOS Receive STS-1 Telecom Bus – Channel 2 – Output Data Bus pin number 1: The exact function of this ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET AE12 STS1RXD_D3_2 O RXHDLCDAT_3_2 O SSE_NEG IO O AG10 STS1RXD_D4_2 O RXHDLCDAT_4_2 RXOHIND_2 CMOS Receive STS-1 Telecom Bus – Channel 2 – Output Data Bus pin number 3: CMOS TTL/CMOS The ...
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XRT94L33 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET Rev.1.2.0. AF12 STS1RXD_D5_2 O RXHDLCDAT_5_2 RXDS3FP_2 AG11 STS1RXD_D6_2 O RXHDLCDAT_6_2 RXDS3DATA_2 CMOS Receive STS-1 Telecom Bus – Channel 2 – Output Data Bus pin number 5: The exact function of this ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET AG12 STS1RXD_D7_2 O RXHDLCDAT_7_2 RXDS3CLK_2 CMOS Receive STS-1 Telecom Bus – Channel 2 – Output Data Bus pin number 7: The exact function of this output pin depends upon whether the ...
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XRT94L33 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET Rev.1.2.0. AD5 RxTOHClk O AC7 RxTOHValid O AE4 RxTOH O AB8 RxTOHFrame ECEIVE RANSPORT VERHEAD NTERFACE CMOS Receive TOH Output Port – Clock Output: This output ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET AD7 RxLDCCVAL O AE5 RxLDCC O AD8 RxE1F1E2FP O CMOS Receive – Line DCC Output Port – DCC Value Indicator Output pin: This output pin, along with the “RxTOHClk” and the ...
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XRT94L33 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET Rev.1.2.0. AC9 RxE1F1E2 O AC8 RxSDCC O CMOS Receive – Order-Wire Output Port – Output Pin: This output pin, along with “RxE1F1E2Val”, “RxE1F1F2FP, and the “RxTOHClk” output pins function as the ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET AD6 RxSDCCVAL O AF4 RxE1F1E2VAL O AE6 RXPOH O CMOS Receive – Section DCC Output Port – DCC Value Indicator Output pin: This output pin, along with the “RxTOHClk” and the ...
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XRT94L33 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET Rev.1.2.0. AG4 RXPOHCLK O AE7 RXPOHFRAME O AD9 RXPOHVALID O AF5 RxPOH_0 O AG5 RxPOH_1 AF8 RxPOH_2 CMOS Receive AU-4/VC-4/STS-3c Mapper POH Processor Block – Path Overhead Output Port – Clock ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET AE8 RxPOHClk_0 O AE9 RxPOHClk_1 AG6 RxPOHClk_2 AF6 RxPOHFrame_0 O AD10 RxPOHFrame_1 AE10 RxPOHFrame_2 AC10 RxPOHValid_0 O AF7 RxPOHValid_1 AC11 RxPOHValid_2 AD11 LOF O AF9 SEF O CMOS Receive SONET POH ...
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XRT94L33 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET Rev.1.2.0. AG7 LOS O W25 GPI0_0 I/O AC27 GPIO_1 I/O CMOS Receive STS-3 LOS (Loss of Signal) Defect Indicator: This output pin indicates whether or not the Receive STS-3 TOH Processor ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET V23 GPIO_2 I/O AB26 GPIO_3 I/O Y25 GPIO_4 I/O TTL/CMOS General Purpose Input/Output pin This input pin can be configured to function as either an input or output pin by writing ...
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XRT94L33 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET Rev.1.2.0. AC26 GPIO_5 I/O W24 GPIO_6 I/O AA25 GPIO_7 I/O TTL/CMOS General Purpose Input/Output pin This input pin can be configured to function as either an input or output pin by ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET E7 REFCLK34 I D5 REFCLK51 I F7 REFCLK45 I F5 TDO O F4 TDI I D3 TRST LOCK NPUTS TTL E3 Reference Clock Input for the Jitter Attenuator ...
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XRT94L33 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET Rev.1.2.0. E4 TCK I E5 TMS I U6 RXCAPP I U5 RXCAPN I W6 RXCAPP_R I W5 RXCAPN_R I H5 REFSEL_L I TTL Test clock: Boundary Scan clock input Note: This ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET K4 SFM I J3 Test Mode I G2 FL_TSTCLK O J2 ANALOG O N1 VDCTST1 O N2 VDCTST2 O TTL Single Frequency Mode (SFM) Select: This input pin permits the user ...
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XRT94L33 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET Rev.1.2.0. K1 N/C AA1 N/C V3 N/C AB1 N/C AA2 N/C AC1 N/C R1 N/C AB2 N/C AC2 N/C T1 N/C AC4 N/C AB5 N/C AD4 N/C AC5 N/C AB7 N/C ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET N23 Analog VDD Pins _ N25 Digital VDD AE1 AE2 AF3 AB9 ...
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XRT94L33 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET Rev.1.2. 110 xr ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET G6 Digital Ground AF1 AF2 AA6 AB6 AE3 AG1 AG2 AB13 AB14 AB15 AG26 AF26 AB22 AA22 AE25 AG27 AF27 T22 R22 P22 N22 M22 B27 B26 G22 ...
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XRT94L33 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET Rev.1.2. Analog Ground L6 T4 N24 N26 112 xr ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET 1.0 XRT94L33 ARCHITECTURE The XRT94L33 can be configured to operate in any of the following modes for ATM and PPP Applications • The 1-Channel STS-3c and Channel DS3/E3 ...
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XRT94L33 Rev.1.2.0. Figure 1 indicates that the XRT94L33 consists of the following functional blocks. • The Receive STS-3 PECL Interface Block • The Receive STS-3 Telecom Bus Interface Block • The Receive STS-3 TOH Processor Block • The Receive STS-3c ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET 1.1 STS-3 TOH P HE ECEIVE The purpose of the “Receive STS-3 TOH Processor” block is to perform the following functions. • To receive an STS-3 signal from the ...
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XRT94L33 Rev.1.2.0. 1.1 ATM C HE ECEIVE ELL The purpose of the “Receive ATM Cell Processor” block is to extract out the data (being carried by the incoming STS-3c SPE data-stream) and to perform the following operations on ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET 1.1 ATM C HE RANSMIT ELL The purpose of the “Transmit ATM Cell Processor” block is to read out the contents of “user” cells that have been written into ...
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XRT94L33 Rev.1.2.0. 1.1. STS-3/12 TOH P HE RANSMIT The purpose of the “Transmit STS-3 TOH Processor” block is to perform the following functions. • To generate and insert the TOH (for the “outbound” STS-3c signal) prior to transmission ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET Figure 2 The Functional Block Diagram of the XRT94L33 when it has been configured to operate in the 1-Channel STS-3 ATM UNI/PPP Mode STS-3/12 STS-3/12 PECL Transmit PECL Transmit Interface Interface ...
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XRT94L33 Rev.1.2.0. Each of these functional blocks is briefly discussed below. These functional blocks will be discussed in considerable detail throughout this data sheet. 1.2 LOCK YNTHESIZER The purpose of the Clock Synthesizer block is to ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET • To optionally transmit the AIS-P indicator, in the down-stream direction (towards the Receive ATM Cell or Receive PPP Packet Processor Blocks) anytime (and for the duration that) the Receive SONET ...
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XRT94L33 Rev.1.2.0. 1.2 ATM C HE RANSMIT ELL The purpose of the “Transmit ATM Cell Processor” block is to read out the contents of “user” cells that have been written into the “TxFIFO” (via the Transmit UTOPIA Interface ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET 1.2. STS-3 TOH P HE RANSMIT The purpose of the “Transmit STS-3 TOH Processor” block is to perform the following functions. • To generate and insert the TOH (for ...
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XRT94L33 Rev.1.2.0. • Servicing of various interrupts. Each of these operations (between the microprocessor and the XRT94L33) will be discussed in some detail, throughout this data sheet. Figure 3 Simple Block Diagram of Microprocessor Interface block of XRT94L33 A[14:0] A[14:0] ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET Table 1 Description of the Microprocessor Interface Pins whenever the Microprocessor Interface has been configured to operate in the Intel Asynchronous Mode AME IN YPE ...
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XRT94L33 Rev.1.2.0. constant across the two modes. Error! Reference source not found. describes the role of some of these signals when the Microprocessor Interface is operating in the Intel Mode. Likewise 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET 126 ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET Table 4 describes the role of these signals when the Microprocessor Interface is operating in the Motorola Mode. Table 2 Description of the Microprocessor Interface Signals that exhibit constant roles in ...
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XRT94L33 Rev.1.2.0. Table 4 Pin Description of the Microprocessor Interface Signals while the Microprocessor Interface is operating in the Motorola Mode QUIVALENT IN YPE N M AME IN OTOROLA E NVIRONMENT ALE_A AS ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET 1.3.2 ATA CCESS ODES As mentioned earlier, the Microprocessor Interface block supports data transfer between the XRT94L33 and the µC/µP (e.g., “Read” and “Write” operations) via two modes: ...
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XRT94L33 Rev.1.2.0. Figure 4 Behavior of Microprocessor Interface signals during an “Intel-type” Programmed I/O Read Operation ALE_AS ALE_AS A[14:0] A[14:0] CS* CS* D[7:0] D[7:0] RDB_DS RDB_DS WRB_RW WRB_RW WRB_RW Rdy_Dtck Rdy_Dtck 1.3.3 NTEL ODE RITE ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET Figure 5 Behavior of the Microprocessor Interface Signals, during an “Intel-type” Programmed I/O Write Operation ALE_AS A[14:0] CS* D[7:0] RdB_DS WRB_RW 1.3.4 P I/O A ROGRAMMED CCESS IN THE If the ...
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XRT94L33 Rev.1.2.0. Figure 6 Illustration of the Behavior of Microprocessor Interface signals, during a “Motorola-type” Programmed I/O Read Operation ALE_AS A[14:0] CS* D[7:0] RDB_DS WRB_RW Rdy_Dtck 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET Address of Target Register Not Valid ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET 1.3.4 OTOROLA ODE Whenever a Motorola-type µC/µP wishes to write a byte or word of data into a register or buffer location, within the UNI, it should ...
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XRT94L33 Rev.1.2.0. Figure 7 Illustration of the Behavior of the Microprocessor Interface signal, during a “Motorola-type” Programmed I/O Write Operation ALE_AS A[14:0] CS* D[7:0] RDB_DS WRB_RW Rdy _ Dtck 1.4 INTERRUPT STRUCTURE WITHIN THE XRT94L33 ATM UNI/PPP IC The XRT94L33 ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET Table 6 List of all of the Possible Conditions that can Generate Interrupts within the XRT94L33 ATM UNI/PPP Device Functional Block Operation Control Block Receive STS-3 TOH Processor Block Receive STS-3c/SONET ...
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XRT94L33 Rev.1.2.0. Receive ATM Cell Processor Block Transmit ATM Cell Processor Block Receive PPP Processor Block Transmit PPP Processor Block The XRT94L33 ATM UNI/PPP comes equipped with the following registers to support the servicing of this wide array of potential ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET Table 7 A Listing of the XRT94L33 ATM UNI/PPP Device Interrupt Block Registers Operation Interrupt Status Register – Byte 0 Operation Interrupt Enable Register – Byte 0 Operation Block Interrupt Status ...
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XRT94L33 Rev.1.2.0. Table 8 A Listing of the XRT94L33 ATM UNI/PPP Device Interrupt Block Registers Receive SONET POH - Path Interrupt Enable Register – Byte 0 – Channel N-1 DS3/E3 Framer Block – Block Interrupt Enable Register – Channel N-1 ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET 1.4 XRT94L33 ATM UNI/PPP D ENERAL LOW OF When any of the conditions, presented in Figure 6 occurs (if their Interrupt is enabled), then the XRT94L33 will generate an ...
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XRT94L33 Rev.1.2.0. Each of the “Operation Block Interrupt Status” Registers presents the “interrupt-request” status of each functional block, within the chip. The purpose of these two registers is to help the µC/µP identify which functional block(s) has requested the interrupt. ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET STEP 2 – INTERRUPT SERVICE ROUTING BRANCHING: AFTER READING THE OPERATION BLOCK INTERRUPT STATUS REGISTERS The contents of the Operation Block Interrupt Status Registers permit the user to identify which of ...
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XRT94L33 Rev.1.2.0. 4. The XRT94L33 will negate the “INT*” (Interrupt Request) output pin. Once these events have occurred, then (as far as the XRT94L33 is concerned) the interrupt has been serviced. 1.4.1 NTERRUPT ERVICING FOR THE If the ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET Operation Channel Interrupt Indicator – Receive STS-3c/SONET POH Processor Block (Address = 0x0120 Unused Receive STS- 3c POH Processor Channel Interrupt Indication ...
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XRT94L33 Rev.1.2.0. Table 10 List of “Source-Level” Interrupt Status Registers that should be read, once “Interrupting” Channel has been identified NTERRUPTING UNCTIONAL HE B LOCK Receive ATM Cell Processor Receive ATM Interrupt Status Register – Byte 1 ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET 1.5 AN OVERVIEW OF POSSIBLE CONFIGURATION OPTIONS IN THE XRT94L33 The XRT94L33 can be configured to function a wide variety of operating modes. summarizes and describes the procedure that one should ...
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XRT94L33 Rev.1.2.0. Configuring the XRT94L33 to operate in the “1-Channel STS-3c (with 0 to 2-Channel DS3/E3) ATM UNI/PPP Mode. To configure the XRT94L33 to operate in this mode execute the following two steps. STEP 1 - SET BITS 1 AND ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET Figure 9 presents the functional block diagram of the XRT94L33 configured to operate in this mode. 147 XRT94L33 Rev.1.2.0. ...
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XRT94L33 Rev.1.2.0. Figure 9 Illustration of the XRT94L33, when it is configured to operate in the 1-Channel STS-3 ATM UNI/PPP Mode STS-3/12 STS-3/12 PECL Transmit PECL Transmit Interface STS-3 Interface STS-3 Block TOH Block TOH Processor Processor STS-3/12 STS-3/12 Block ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET Setting this bit-field to “0” configures the XRT94L33 to operate in the ATM UNI Mode. Conversely, setting this bit-field to “1” configures the XRT94L33 to operate in the PPP Mode. Please ...
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XRT94L33 Rev.1.2.0. 2.2 THE TRANSMIT DIRECTION If a given channel (or the entire device) is configured to operate in the ATM Mode, then the purpose of the Transmit section within the XRT94L33 1-Channel STS-3c/STS-3 ATM UNI device is to allow ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET The Transmit SONET POH Processor or Transmit STS-3c POH Processor block will accept these ATM cells and will map them into either an STS-1 or STS-3c SPE, respectively. Additionally, the Transmit ...
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XRT94L33 Rev.1.2.0. 2.2.1.1 THE PINS OF THE TRANSMIT UTOPIA BUS INTERFACE The ATM Layer processor will interface to the Transmit UTOPIA Interface block via the following pins. • TxUData[15:0] - Transmit UTOPIA Data Bus Input pins • TxUAddr[4:0] - Transmit ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET TxUClkO – Transmit UTOPIA Interface Block Clock Output signal If the “Transmit UTOPIA Clock De-Skewing” PLL is enabled, then the ATM Layer Processor can use this signal to clock out the ...
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XRT94L33 Rev.1.2.0. Transmit UTOPIA Control Register – Byte 0, Address = 0x0583 UTOPIA Multi-PHY Back-to- Back Polling Level 3 Mode Enable Disable R/W R/W R Setting this bit-field to ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET Table 11 The Relationship between the contents of “Transmit UTOPIA Data Bus Width[1:0] within the Transmit UTOPIA Control Register and the operating width of the Transmit UTOPIA Data bus T UTOPIA ...
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XRT94L33 Rev.1.2.0. Table 12 The Relationship between the contents of Bits 1 and 0 (Cell_Size_Sel[1:0]) within the Transmit UTOPIA Control Register, and the number of octets per cell that will be processed by the Transmit UTOPIA Interface blocks per assertion ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET Figure 11 Timing Diagram of various Transmit UTOPIA Interface block signals, when the Transmit UTOPIA Interface block is operating in the “Cell Level Handshaking” Mode TxUClk TxUClav TxUEnB ...
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XRT94L33 Rev.1.2.0. Transmit UTOPIA Control Register – Byte 0, Address = 0x0583 UTOPIA Multi-PHY Back-to- Back Polling Level Mode Enable R/W R/W R Note: This configuration setting does not ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET Note: The Transmit UTOPIA Interface block will sample and latch the state of the TxUSoC input pin upon the rising edge of TxUClk. Therefore, if the TxUClk to TxUSoC output delay ...
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XRT94L33 Rev.1.2.0. Figure 13 Flow Chart depicting the approach that the ATM Layer Processor should take when writing ATM Cell Data into the Transmit UTOPIA Interface block, when the XRT94L33 is operating in the Single PHY Mode START Check the ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET Figure 14 Timing Diagram of ATM Layer Processor writing ATM Cell data into the Transmit UTOPIA Data Bus, (Single - PHY Mode TxUClk TxUClav TxUEnB * TxUData [15:0] ...
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XRT94L33 Rev.1.2.0. XRT94L33 is operating in the Multi-PHY mode, the Transmit UTOPIA Interface block will support two kinds of operations with the ATM Layer processor: • Polling for “available” UNI (PHY Layer) devices. • Selecting which UNI (out of several ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET Transmit UTOPIA Port Number Register (Address = 0x0597 Unused R/O R/O R This step configures an internal “Transmit UTOPIA Address ...
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XRT94L33 Rev.1.2.0. STEP 2b – Set Bits 0 through 4 (“Tx_UTOPIA_Addr[4:0]”) within the “Transmit UTOPIA Address” Register to the desired “Multi-PHY” Address value for this channel [b4, b3, b2, b1, b0]; as depicted below. Transmit UTOPIA Address Register (Address = ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET This step configures the Transmit UTOPIA Address, of the value [C4, C3, C2, C1, C0 assigned to STS- 3c Channel 2. Notes: 1. During this step, the user can ...
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XRT94L33 Rev.1.2.0. 2.2.1.3.8 ATM Layer Processor “polling” of the UNIs, in the Multi-PHY Mode In this section, the various Multi-PHY Operations (e.g., polling and selection for writing) will be first discussed for a “Conceptual Multi-PHY” System, and then later, specifically ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET Table 13 UTOPIA Address Values of the UTOPIA Interface blocks illustrated in Figure 26. B LOCK Transmit UTOPIA Interface block - UNI #1 Receive UTOPIA Interface block - UNI #1 Transmit ...
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XRT94L33 Rev.1.2.0. output signal “low” if its TxFIFO is too full and is incapable of receiving one more complete cell of data from the ATM Layer processor. When UNI #2 has been selected for “polling”, UNI #1 will continue to ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET XRT94L33 can be thought of as consisting of four ATM UNIs within a single package (one for each STS-3c port within the device important to note that although the ...
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XRT94L33 Rev.1.2.0. Figure 18: Timing Diagram of the Transmit UTOPIA Data and Address Bus signals, during the “Multi- PHY” UNI Device Selection and Write Operations 1 2 TxUClk 0x1F TxUAddr[4:0] 0x00 0x00 TxUClav TxUEnB* Cell Transmitted to 0x02 W23 TxUData[15:0] ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET Transmit UTOPIA Control Register – Byte 0, Address = 0x0483 UTOPIA Multi-PHY Back-to- Back Polling Level Mode Enable R/W R/W R ...
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XRT94L33 Rev.1.2.0. Figure 20 presents a simple block diagram of the Transmit ATM Cell Processor block (with the external pins indicated). Figure 20: Simple Illustration of the Transmit ATM Cell Processor Block and the Associated External Pins TxCellTxed TxGFCClk TxGFCMSB ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET 2.2 RANSMIT ATA ATH All ATM cells that successfully pass through “Parity Checking” and “User Cell Filtering” will be processed via the “HEC Byte Calculation & ...
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XRT94L33 Rev.1.2.0. Transmit ATM Cell Processor Block – Transmit ATM Control Register – Byte 2 (Address = 0xNF01 R/O R/O R Figure 21: Functional Block Diagram of the Transmit ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET of ATM cell data also sampling and latching the value of the corresponding parity bit (via the “TxUPrty” input pin). All sampled byte/words and their corresponding sampled parity value ...
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XRT94L33 Rev.1.2.0. Transmit ATM Control – Byte 0 Register (Address = 0xNF03 HEC Byte HEC Byte Parity Check Invert Check Enable Enable R/W R/W R Setting this bit-field to ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET Transmit ATM Cell Processor – Interrupt Enable Register (Address = 0xNF0F Unused Cell Extraction Interrupt Enable R/O R/O R ...
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XRT94L33 Rev.1.2.0. Transmit ATM Cell Processor – Parity Error Count Register – Byte 3 (Address = 0xNF34 RUR RUR RUR Transmit ATM Cell Processor – Parity Error Count Register ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET Figure 22: Illustration of the “Transmit ATM Cell Processor” Functional Block Diagram with the “Transmit User-Cell Filter” block highlighted TxFIFO TxFIFO Transmit UTOPIA Interface Block Main Data Path The Transmit ATM ...
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XRT94L33 Rev.1.2.0. Figure 23: An Illustration of the Configuration of the Four Transmit User Cell Filters within the Transmit ATM Cell Processor block From Parity Checker and Insertion Memory Blocks Each of these four (4) User Cell filters can be ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET 2.2.6 NABLING ISABLING THE The Transmit ATM Cell Processor block permits the user to either enable or disable each of the four Transmit User Cell Filters. The user can ...
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XRT94L33 Rev.1.2.0. Bit 1 – Discard Cell Enable This bit-field permits the user to configures the “Transmit User Cell” filter (within the Transmit ATM Cell Processor block) either discard or not discard a given cell that complies with the “user-defined” ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET 2.2.6 RANSMIT SER ELL The four User Cell Filter – Pattern Registers permit the user to specify the Header Byte Pattern for the Transmit User Cell Filter. ...
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XRT94L33 Rev.1.2.0. 2.2.6 RANSMIT SER ELL The four User Cell Filter – Check Registers permit the user to specify which bits (within the Header bytes of User Cells) will be checked and compared with the contents ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET Transmit ATM Filter # Check – Header Byte 4 (Address = 0xNF4B, 0xNF5B, 0xNF6B, 0xNF7B R/W ...
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XRT94L33 Rev.1.2.0. Transmit ATM Filter # – Filtered Cell Counter – Byte 0 (Address = 0xNF4F, 0xNF5F, 0xNF6F, 0xNF7F RUR RUR RUR ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET 2.2.6 RANSMIT ELL NSERTION The Transmit ATM Cell Processor block consists of a “Transmit Cell Insertion Buffer/Processor” block. Figure 24 presents the functional block diagram of ...
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XRT94L33 Rev.1.2.0. Figure 25: Byte-Format of the ATM Cell that loaded into the “Transmit Cell Insertion” Memory As a consequence, the user must write in a total of 14 “32-bit words” into the “Transmit Cell Insertion” buffer ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET STEP 1b – Write a “1” into Bit 2 (Insertion Memory RESET*), within the “Transmit ATM Cell – Memory Control” Register; as depicted below. Transmit ATM Cell – Memory Control Register ...
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XRT94L33 Rev.1.2.0. The user can enable the “Transmit Cell Insertion” Interrupt by setting Bit 4 (Cell Insertion Interrupt Enable), within the “Transmit ATM Cell Processor – Interrupt Enable” Register to “1” as indicated below. Transmit ATM Cell Processor – Interrupt ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET STEP 4 – Write the very first 32-bit word of this new ATM cell into the “Transmit Cell Insertion Buffer”. This is accomplished by executing the following four sub-steps. STEP 4a ...
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XRT94L33 Rev.1.2.0. STEP 4d – Write the contents of the fourth byte (of this new ATM cell) into the Transmit ATM Cell – Insertion/Extraction Memory Register – Byte 0; as depicted below. Transmit ATM Cell – Insertion/Extraction Memory Register – ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET 2.2.6 RANSMIT ELL XTRACTION The Transmit ATM Cell Processor block consists of a “Transmit Cell Extraction Buffer/Processor” block. Figure 26 presents the functional block diagram of ...
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XRT94L33 Rev.1.2.0. The Format of the ATM Cell that is Read from the “Transmit Cell Extraction” Buffer As the user reads out the contents of an ATM cell from the “Transmit Cell Extraction” Buffer (via the Microprocessor Interface), they will ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET STEP 1a – Write a “0” into Bit 4 (Extraction Memory RESET*) within the “Transmit ATM Cell – Memory Control” Register; as depicted below. Transmit ATM Cell – Memory Control Register ...
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XRT94L33 Rev.1.2.0. Conversely, if Bit 3 is set to “0”, then the “Transmit Cell Extraction Buffer” does not contain an ATM cell that needs to be read. At this point, the Microprocessor Interface should continue to poll the state of ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET Transmit ATM Cell – Insertion/Extraction Memory Register – Byte 3 (Address = 0xNF14 R/W R/W R Note: In this case, ...
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XRT94L33 Rev.1.2.0. 2.2.6. DLE ELL ENERATOR The Transmit ATM Cell Processor block consists of a “Idle Cell Generator” block. Figure 28 presents the functional block diagram of the “Transmit ATM Cell Processor block with the ...
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DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET STEP 1 – Write the “desired value” for header byte 1 (within these Idle Cells) into the “Transmit ATM Cell – Idle Cell Header Byte 1 Register; as depicted below. Transmit ...
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XRT94L33 Rev.1.2.0. STEP 5 – Write the “desired value” for the payload byte (within these Idle Cells) into the “Transmit ATM Cell – Idle Cell Payload Byte Register; as depicted below. Transmit ATM Cell – Idle Cell Payload Byte Register ...