XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 403

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
Figure 97 Illustration of the “Functional Block Diagram” of the Receive ATM Cell Processor Block with
the HEC Byte Verification” block highlighted
The HEC Byte Verification block will receive an un-delineated stream of ATM cells, from the Receive STS-3c
POH Processor block. As the HEC Byte Verification block receives this data-stream it is responsible for
performing the following two functions, within the Receive ATM Cell Processor block
• Cell Delineation
• HEC Byte Verification
Each of these functions is described in some detail below.
2.3.4.1.1
As the Receive STS-3c POH Processor block receives the incoming STS-3c SPE data, the contents of these
STS-3c SPEs will be extracted out and will be routed to the Receive ATM Cell Processor block for further
processing.
In ATM applications, the contents of each of these STS-3c SPEs are ATM cells. As the HEC Byte Verification
block receives this stream of ATM cells, this ATM cell data will initially be “unframed”. Therefore, the HEC
Byte Verification block will have to use the “HEC Byte” Cell-Delineation algorithm in order to locate the
boundaries of these cells. The HEC Byte Cell Delineation algorithm contains three states: HUNT, PRESYNC
and SYNC, as depicted in the State Machine Diagram in Figure 98. Each of these three states is discussed
below.
Receive UTOPIA
Interface Block
Main Data Path
RxFIFO
RxFIFO
Acquiring and Maintaining Cell Delineation with the Incoming ATM Cell Data-Stream
Calculation
Calculation
Parity
Block
Parity
Block
De-Scrambler
Cell Payload
De-Scrambler
User Cell
Cell Payload
User Cell
Idle Cell
Filter
Block
Idle Cell
Block
Filter
Block
Filter
Block
Filter
403
Cell Extraction
Cell Insertion
Cell Extraction
Cell Insertion
Processor
Processor
Verification
Processor
Processor
HEC Byte
Verification
Buffer/
Buffer/
HEC Byte
Buffer/
Buffer/
Block
Receive GFC
Block
Nibble-Field
Receive GFC
Nibble-Field
Output I/F
Output I/F
Microprocessor
Microprocessor
STS-3c/STS-12c
Processor Block
From Receive
Interface
Interface
Block
Block
POH
XRT94L33
Rev.1.2.0.