XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 170

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT94L33
Rev.1.2.0.
Figure 18: Timing Diagram of the Transmit UTOPIA Data and Address Bus signals, during the “Multi-
PHY” UNI Device Selection and Write Operations
Notes regarding Figure 18:
1. The Transmit UTOPIA Data bus is configured to be 16 bits wide. Hence, the data, which the ATM Layer
processor places on the Transmit UTOPIA Data bus, is expressed in terms of 16-bit words (e.g., W0 - W26).
2. The Transmit UTOPIA Interface Block is configured to handle 54 bytes/cell. Hence, Figure 29 illustrates
the ATM Layer processor writing 27 words (e.g., W0 through W26) for each ATM cell.
In Figure 29, the ATM Layer processor is initially writing ATM cell data to the Transmit UTOPIA Interface
block within UNI #2 (TxUAddr[4:0] = 0x02). However, the ATM Layer processor is also polling the Transmit
UTOPIA Interface block within UNI #1 (TxAddr[4:0] = 0x00) and the “NULL” address of 0x1F. The ATM Layer
processor completes its writing of the cell to UNI #1 at clock edge #4. Afterwards, the ATM Layer processor
will cease to write any more cell data to UNI #1, and will begin to write this data into UNI #2 (TxUAddr[4:0] =
0x02). The ATM Layer processor will indicate its intentions to select a new UNI device for writing by negating
the TxUEnB* signal, at clock edge #5 (see the shaded portion of Figure 29). At this time, UNI #1 will notice
two things:
1. The UTOPIA Address for the Transmit UTOPIA Interface block, within UNI #1 is on the Transmit UTOPIA
Address bus (TxUAddr[4:0] = 0x00).
2. The TxUEnB* signal has been negated.
UNI #1 will interpret this signaling as an indication that the ATM Layer processor is going to be performing
write operations to it. Afterwards, the ATM Layer processor will begin to write ATM cell data into Transmit
UTOPIA Interface block, within UNI #1.
2.2.1.4
B
If the Transmit UTOPIA Interface block has been configured to operate in the UTOPIA Level 3 mode, then it
can be configured to support “Back-to-Back” polling.
UTOPIA Level 2 specifications mandate that the ATM Layer Processor interleave the application of UTOPIA
addresses with the “NULL” address of 0x1F.
If “Back-to-Back” polling is selected, then the ATM Layer Processor does not need to interleave the
application of UTOPIA addresses with the “NULL” address. Instead, the ATM Layer Processor can poll each
of the UNIs, by applying a different “UTOPIA Address” value, with each cycle of “TxUClk” (e.g., in a “Back-to-
Back” Manner).
The user can configure the “Transmit UTOPIA Interface” block to support “Back-to-Back” polling by setting bit
5 (Back-to-Back Polling Enable) within the “Transmit UTOPIA Control” Register, to “1” as depicted below.
ACK
-
TO
-B
ACK
UTOPIA L
TxUData[15:0]
TxUAddr[4:0]
P
TxUEnB*
TxUClav
TxUSoC
TxUClk
OLLING
EVEL
W23
0x00
1
Cell Transmitted to 0x02
3 O
0x00
0x1F
W24
PERATION OF THE
2
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
W25
0x02
3
0x02
0x1F
W26
4
T
0x00
RANSMIT
5
170
0x00
0x02
W0
6
Cell Transmitted to 0x00
UTOPIA I
0x02
0x1F
W1
7
0x00
W2
NTERFACE
8
0x00
0x02
W3
9
B
0x02
W4
0x1F
LOCK
10
0x02
W5
11
xr
0x02
0x00
W6
12