XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 395

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
2.3.3.1.1
2.3.3.1.2
2.3.3.1.3
2.3.3.1.4
2.3.3.1.5
2.3.3.2
2.3.3.2.1
2.3.3.2.2
The Receive SONET POH Processor block is capable of detecting the REI-P indicator, within the incoming
STS-1 SPE data-stream. As the Receive SONET POH Processor block receives a given STS-1 SPE data-
stream, it will monitor the contents within Bits _ through _ in the G1 byte. The bit-format of the G1 byte is
presented below in Figure 93
Figure 93 Bit format of the G1 Byte
Figure 93 indicates that Bits _ through _, within the G1 byte are allocated for the REI-P function.
The role of the REI-P bit-fields was described in some detail, in Section _. This section indicates that the
remote PTE will set the “REI-P” value (within the G1 byte) to “0” during “un-erred” conditions. However, the
remote PTE will typically set the “REI-P” value to a value (ranging from “1” to “8”) during “erred” conditions.
If the Receive SONET POH Processor block receives an STS-1 SPE, that contains a “non-zero” value of REI-
P, then it will do the following.
1. It will generate the “Detection of REI-P Event” Interrupt.
Note:
Receive SONET Path – SONET Receive Path Interrupt Status – Byte 1 (Address = 0xN18A)
2. It will increment the “Receive SONET Path – REI-P Error Count” Registers
Note:
Unused
B
R/O
IT
0
7
The Receive SONET POH Processor block will indicate this by, pulling the “INT*” output pin “LOW” and by
These registers are actually 32-bit registers, which are located at Direct Address locations 0xNA9C through
setting Bit 6 (Detection of REI-P Event Interrupt Status), within the “Receive SONET Path – SONET Receive
Path Interrupt Status – Byte 1” to “1” as depicted below.
0xNA9F. The bit-format of these registers is presented below.
PROCESSING/HANDLING THE G1 BYTE
Handling Incrementing Pointer Adjustment Events
Handling NDF (New Data Flag) Events
Handling Decrementing Pointer Adjustment Events
LOP-P DECLARATION AND CLEARANCE CRITERIA
AIS-P DECLARATION AND CLEARANCE CRITERIA
RDI-P DETECTION AND CLEARANCE CRITERIA
DETECTING/FLAGGING REI-P EVENTS
REI-P Event
Detection of
Interrupt
Status
B
RUR
IT
1
6
Change in
Condition
UNEQ-P
Interrupt
Defect
Status
B
RUR
IT
0
5
Change in
Condition
Interrupt
PLM-P
Defect
Status
B
RUR
IT
0
4
395
Interrupt
New C2
Status
B
RUR
Byte
IT
0
3
Change in
Condition
Unstable
Interrupt
C2 Byte
Defect
Status
B
RUR
IT
0
2
Change in
Condition
Unstable
Interrupt
Defect
Status
RDI-P
B
RUR
IT
0
1
XRT94L33
RDI-P Value
Interrupt
Status
Rev.1.2.0.
B
RUR
New
IT
0
0