XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 251

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
Figure 44: A Simple Illustration of the “External Circuit” being interfaced to the “TxPOH Input Port”
Note:
• Whenever the “external circuit” samples both the “TxPOHEnable_n” and “TxPOHFrame_n” output pins
“high”, then it should enter a “WAIT STATE” (e.g., where it will wait for _ periods of “TxPOHClk_n” to elapse).
Afterwards, the external circuit should exit this “WAIT STATE” and then place the very first bit (e.g., the most
significant bit) of the “outbound” Z5 byte onto the “TxPOH_n” input pin, upon the very next falling edge of
“TxPOHClk_n”. This data bit will be sampled and latched into the “Transmit STS-3c POH Processor” block
circuitry, upon the very next rising edge of “TxPOHClk_n”.
Note:
• Afterwards, the “external circuit” should serially place the remaining seven bits (of the Z5 byte) onto the
“TxPOH_n” input pin, upon each of the next seven falling edges of “TxPOHClk_n”.
• The “external circuit” should then revert back to continuously sampling the states of the “TxPOHEnable_n”
and “TxPOHFrame_n” output pins and repeat the above-mentioned process.
2.2.7.3.11
FORCING POINTER ADJUSTMENTS AND NDF EVENTS VIA SOFTWARE
The “Transmit STS-3c POH Processor” block permits the user to insert pointer adjustments or NDF events
into the “outbound” STS-3c data stream. Specifically, the Transmit STS-3c POH Processor block permits the
user to implement the following “pointer-related” features.
• To force the pointer to shift to an “arbitrary value”
• To configure the Transmit STS-3c POH Processor block to only insert pointer-adjustment or NDF events, if
no pointer-adjustment (NDF or otherwise) events have occurred within the last three (3) STS-3c framing
periods.
The “TxPOHIns_n” line (in Figure 44) is “dashed” because controlling this signal is not necessary if the user has
This “WAIT STATE” period is necessary because the Z5 byte is the ninth byte within the POH.
executed “STEP 1” above.
POINTER-ADJUSTMENT/NDF OPTIONS
XRT95L34 Device
TxPOHEnable_n
TxPOHFrame_n
TxPOHClk_n
TxPOHIns_n
TxPOH_n
251
TxPOHData_OUT
TxPOHFrame_IN
TxPOHEnable_IN
TxPOH_INSERT
TxPOHClk_IN
External Circuit
XRT94L33
Rev.1.2.0.