XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 431

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
Receive ATM Cell Processor – Interrupt Enable Register (Address = 0xN70F)
Once a cell (residing within the Receive Cell Insertion Buffer) has been inserted into the “Receive Input Data
Path”, then the XRT94L33 will do all of the following:
• It will toggle the “INT*” output pin “LOW”.
• It will set Bit 4 (Cell Insertion Interrupt Status), within the Receive ATM Cell Processor – Interrupt Status
Register; to “1” as depicted below.
Receive ATM Cell Processor – Interrupt Status Register (Address = 0xN70B)
At this point, the user can now proceed on with STEP 3.
STEP 3 – Inform the “Receive Cell Insertion Processor” that the very next 32-bit word to be written
into the “Receive Cell Insertion Buffer” is the first word of a new ATM cell.
This is accomplished by writing the value “1” into Bit 0 (Insertion Memory Write SoC), within the “Receive
ATM Cell – Memory Control Register” as depicted below.
Receive ATM Cell – Memory Control Register (Address = 0xN713)
STEP 4 – Write the very first 32-bit word of this new ATM cell into the “Receive Cell Insertion Buffer”.
This is accomplished by executing the following four sub-steps.
STEP 4a - Write the contents of first byte (of this new ATM cell) into the Receive ATM Cell –
Insertion/Extraction Memory Register – Byte 3; as depicted below.
B
B
R/O
R/O
B
IT
IT
R/O
0
0
IT
0
7
7
7
Unused
Unused
B
B
R/O
R/O
IT
IT
0
0
Unused
B
6
6
R/O
IT
0
6
Extraction
Extraction
Interrupt
Interrupt
Enable
Status
B
B
RUR
R/W
Cell
Cell
IT
IT
0
0
5
5
B
R/O
IT
0
5
Insertion
Insertion
Interrupt
Interrupt
Enable
Status
B
B
RUR
R/W
Extraction
Cell
Cell
RESET*
Memory
IT
IT
1
1
B
R/W
4
4
IT
1
4
431
Extraction
Extraction
Overflow
Overflow
Interrupt
Interrupt
Memory
Memory
Enable
Status
Extraction
B
B
RUR
R/W
Cell
Cell
Memory
IT
IT
0
0
CLAV
B
R/W
3
3
IT
0
3
Cell Insertion
Cell Insertion
Overflow
Overflow
Interrupt
Interrupt
Memory
Memory
Enable
Status
Insertion
RESET*
Memory
B
B
RUR
R/W
B
IT
IT
R/W
0
0
IT
1
2
2
2
Detection of
Detection of
HEC Byte
HEC Byte
Interrupt
Interrupt
Enable
Insertion
Status
Memory
ROOM
B
Error
B
Error
RUR
R/W
B
R/W
IT
IT
0
0
IT
1
1
1
1
XRT94L33
Detection of
Detection of
Parity Error
Parity Error
Write SoC
Interrupt
Interrupt
Insertion
Memory
Enable
Status
Rev.1.2.0.
B
B
RUR
R/W
B
R/W
IT
IT
0
0
IT
1
0
0
0