XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 450

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

xr
XRT94L33
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
Rev.1.2.0.
2. Assert the RxUEnB* pin and read the first byte (or word) of the new cell from the Receive UTOPIA
Data Bus.
Once the ATM Layer processor has detected that RxUClav has toggled “high”, then it should assert the
RxUEnB* input pin (e.g., toggling it “low”). Once the Receive UTOPIA Interface block has determined that the
RxUEnB* input pin is “low”, then it will begin to place some cell data onto the Receive UTOPIA Data Bus. If
this first byte (or word) is the beginning of a new ATM cell, then the ATM Layer processor should verify that
this byte (or word) is indeed the beginning of a new cell, by observing the RxUSoC output pin (of the
XRT94L33 IC) pulsing “high” for one clock period of RxUClk.
3. Compute the odd-parity of the byte (or word) that is being read from the Receive UTOPIA Data bus,
and compare the value of this parity bit with that of the RxUPrty output pin.
This operation is optional, but should be done concurrently while checking for the assertion of the RxUSoc
output pin.
When reading in the subsequent bytes (or words) of the cell, the ATM Layer must do the following.
• Repeat Steps 1 and 2.
• The ATM Layer processor should check the RxUClav signal level just as it (the ATM Layer processor) is
reading in the very last byte (or word) of a given cell. If the RxUClav level is “high”, then the ATM Layer
processor should proceed to read in the next cell from the Receive UTOPIA Interface block. However, if the
RxUClav level is “low”, then the ATM Layer processor should halt reading in data, when it reaches the end of
the cell (that it is currently reading in).
• The ATM Layer processor should keep a count on the total number of bytes that have been read in since
the last assertion of the RxUSoC output pin. This will help the ATM Layer processor to determine when it has
reached the boundary of a given cell.
The above-mentioned procedure is also depicted in “Flow Chart Form” in Figure 115 and in Timing Diagram
form in Figure 116.
Figure 115 Flow Chart depicting the approach that the ATM Layer Processor should take when
reading ATM Cell data from the Receive UTOPIA Interface, when the XRT94L33 is operating in the
Single-PHY Mode
450