XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 41

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

xr
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
AG20
AC17
AD17
G25
D27
F25
J24
EIGHTKHZSYNC_0/
EIGHTKHZSYNC_1/
EIGHTKHZSYNC_2/
RXHDLC_CLK_0/
RXHDLC_CLK_1/
RXHDLC_CLK_2/
TxUPRTY/
TxMOD_0
TxPPRTY
TXPERR
TxPEOP
I/O
I
I
I
I
TTL/CMOS
TTL
TTL
TTL
TTL
Transmit
Alignment Input/Receive High-Speed HDLC Controller
Output Interface Block – Clock Output – Channel n:
The exact function of this input pin depends upon (1) whether
the XRT94L33 has been configured to operate in the ATM
UNI/PLCP Mode and (2) whether Channel n has been
configured to operate in the “High-Speed HDLC Controller”
Mode, as described below.
ATM UNI Mode - EIGHTKHZSYNC_n:
Processor Block 8kHz Framing Alignment Input:
This pin only functions in this particular role if the XRT94L33
has been configured to operate in the ATM UNI Mode. For
more information on this pin operating in this mode, please
see the XRT94L33 Pin Description for ATM UNI/PPP
Applications.
High-Speed HDLC Controller Mode - Receive High-Speed
HDLC Controller Output Interface Block - Clock output
signal – Channel n – RxHDLCClk_n:
This output pin functions as the “Receive High-Speed HDLC
Controller Output Interface block – clock output signal for
Channel n. The Receive High-Speed HDLC Controller Output
Interface block outputs the contents of all received HDLC
frames and flag sequence octets via the Receive High-Speed
HDLC Controller Output Interface block – Data Bus output pins
(RxHDLCDat_n[7:0]) upon the rising edge of this clock signal.
The user is advised to configure the terminal equipment to
sample the contents of the RxHDLCDat_n[7:0] output pins
upon the falling edge of this clock signal.
Note:
For Mapper applications, please connect this pin to GND.
For Mapper applications, please connect this pin to GND.
For Mapper applications, please connect this pin to GND.
For Mapper applications, please connect this pin to GND.
41
The user should tie this pin to GND if the DS3/E3
Framer block has NOT been configured to operate
in the “High-Speed HDLC Controller” Mode.
PLCP
Processor
Block
–
Transmit PLCP
8kHz
XRT94L33
Framing
Rev.1.2.0.