XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 148

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XRT94L33IB-L

Manufacturer Part Number
XRT94L33IB-L
Description
IC MAPPER DS3/E3/STS-1 504TBGA
Manufacturer
Exar Corporation
Datasheets

Specifications of XRT94L33IB-L

Applications
Network Switches
Interface
Bus
Voltage - Supply
3.14 V ~ 3.47 V
Package / Case
504-LBGA
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XRT94L33IB-L
Manufacturer:
Exar Corporation
Quantity:
10 000
XRT94L33
Rev.1.2.0.
Figure 9 Illustration of the XRT94L33, when it is configured to operate in the 1-Channel STS-3 ATM
UNI/PPP Mode
Configuring the XRT94L33 to operate in the “1-Channel STS-3 ATM UNI/PPP Mode
To configure the XRT94L33 to operate in this mode execute the following steps.
STEP 1 – SET BITS 1 AND 0 (CONF[1:0]), WITHIN THE OPERATION CONTROL REGISTER – BYTE 3;
TO [1, 1]; AS DEPICTED BELOW.
Operation Control Register – Byte 3 (Address = 0x0100)
STEP 2 – SET BIT 2 (PPP/ATM*), WITHIN THE “OPERATION CONTROL REGISTER- BYTE 0” TO THE
APPROPRIATE VALUE AS DEPICTED BELOW.
Operation Control Register – Byte 0 (Address = 0x0103)
PLL OFF
Transmit
UTOPIA
B
B
R/W
R/W
Microprocessor
IT
IT
X
0
Microprocessor
7
7
Interface
STS-3/12
Interface
STS-3/12
Telecom
Interface
Interface
STS-3/12
Interface
STS-3/12
Telecom
Interface
STS-3/12
PECL
Block
Block
Block
STS-3/12
PECL
Block
Block
Block
Block
Bus
CDR
Block
Bus
CDR
PLL OFF
UTOPIA
Receive
CH_MODE_SEL[3:0]
B
B
R/W
R/W
IT
IT
X
0
6
6
Synthesizer
Synthesizer
Processor
Transmit
Processor
Processor
Transmit
Clock
Block
STS-3
Processor
Block
Receive
TOH
Clock
Block
STS-3
STS-3
Block
Receive
Block
TOH
TOH
STS-3
Block
TOH
B
B
R/W
R/O
IT
IT
X
0
5
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
5
XRT94L33 – Channel 0
Processor
Processor
Transmit
Unused
Processor
Processor
SONET
Receive
SONET
Transmit
SONET
SONET
B
Receive
B
Block
Block
R/W
R/O
POH
POH
Block
Block
POH
POH
IT
IT
0
X
4
4
To Channels 1 and 2
148
Dual Bus
B
B
R/O
R/W
Cell Processor
IT
Cell Processor
0
IT
X
Cell Processor
Cell Processor
Processor
Processor
Transmit
3
Processor
Processor
3
Transmit
Transmit
Receive
From Channels 1 and 2
Receive
Transmit
Receive
Block
Block
Receive
Block
ATM
PPP
Block
PPP
Block
Block
ATM
ATM
Block
PPP
PPP
Block
ATM
PPP/ATM*
Unused
B
B
R/W
R/O
IT
IT
X
0
2
2
POS-PHY
POS-PHY
UTOPIA/
Transmit
Transmit
UTOPIA
Interface
Interface
Interface
Interface
POS-PHY
POS-PHY
UTOPIA/
Transmit
Transmit
Receive
Receive
UTOPIA
Interface
Interface
Interface
Interface
Block
Block
Receive
Block
Receive
Block
Unused
Block
Block
Block
Block
B
B
R/W
R/O
IT
1
IT
0
1
1
xr
CONF[1:0]
SW RESET
B
B
R/W
R/W
IT
IT
1
0
0
0

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